topic Re: Initialize OSC1 PLL on TWR-K70 in Kinetis Microcontrollers

Initialize OSC1 PLL on TWR-K70

gaminn — Mon, 25 Feb 2013 21:05:31 GMT

Hello,

I need to initialize both PLL0 and PLL1 to derive their clock from OSC1. Initialization happens after reset. Can you please provide sample code? My board is TWR-K70.

Re: Initialize OSC1 PLL on TWR-K70

deepakrana — Wed, 27 Feb 2013 04:48:28 GMT

You can check the code example in the link

https://www.freescale.com/webapp/Download?colCode=KINETIS_120MHZ_SC&appType=license&location=null&fpsp=1&WT_TYPE=Snippets,%20Boot%20Code,%20Headers,%20Monitors,%20etc.&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=zip&WT_ASSET=Downloads&sr=3&Parent_nodeId=1322538641013716882290&Parent_pageType=product

In these check for the MCG drivers. See if you can make them to work as per your requirement.

Right now i think both the PLL are working from the clock or you will just need to enable in the driver.

You should be able to work this out.

Cheers !!!

Re: Initialize OSC1 PLL on TWR-K70

gaminn — Sat, 02 Mar 2013 09:31:49 GMT

Thanks, but MCGOUT PLL initialization from OSC1 is not supported by the driver.

// Check if OSC1 is being used as a reference for the MCGOUT PLL

// This requires a more complicated MCG configuration.

// At this time (Sept 8th 2011) this driver does not support this option

if (osc_select && mcgout_select)

{

return 0x80; // Driver does not support using OSC1 as the PLL reference for the system clock on MCGOUT

}

Re: Initialize OSC1 PLL on TWR-K70

deepakrana — Tue, 25 Jun 2013 04:29:22 GMT

HI Martin

Sincere apologies for the delayed response (somehow i missed your reply) if you check the K70 sysinit.c file you will find both the PLL used one for system clock and one for DDR.

Snapshot of the code in the file

/* NOTE: The PLL init will not configure the system clock dividers,

* so they must be configured appropriately before calling the PLL

* init function to ensure that clocks remain in valid ranges.

SIM_CLKDIV1 = ( 0

| SIM_CLKDIV1_OUTDIV1(0)

| SIM_CLKDIV1_OUTDIV2(1)

| SIM_CLKDIV1_OUTDIV3(2)

| SIM_CLKDIV1_OUTDIV4(5) );

/* Initialize PLL0 */

/* PLL0 will be the source for MCG CLKOUT so the core, system, FlexBus, and flash clocks are derived from it */

mcg_clk_hz = pll_init(OSCINIT, /* Initialize the oscillator circuit */

OSC_0, /* Use CLKIN0 as the input clock */

CLK0_FREQ_HZ, /* CLKIN0 frequency */

LOW_POWER, /* Set the oscillator for low power mode */

CLK0_TYPE, /* Crystal or canned oscillator clock input */

PLL_0, /* PLL to initialize, in this case PLL0 */

PLL0_PRDIV, /* PLL predivider value */

PLL0_VDIV, /* PLL multiplier */

MCGOUT); /* Use the output from this PLL as the MCGOUT */

/* Check the value returned from pll_init() to make sure there wasn't an error */

if (mcg_clk_hz < 0x100)

while(1);

/* Initialize PLL1 */

/* PLL1 will be the source for the DDR controller, but NOT the MCGOUT */

pll_1_clk_khz = (pll_init(NO_OSCINIT, /* Don't init the osc circuit, already done */

OSC_0, /* Use CLKIN0 as the input clock */

CLK0_FREQ_HZ, /* CLKIN0 frequency */

LOW_POWER, /* Set the oscillator for low power mode */

CLK0_TYPE, /* Crystal or canned oscillator clock input */

PLL_1, /* PLL to initialize, in this case PLL1 */

PLL1_PRDIV, /* PLL predivider value */

PLL1_VDIV, /* PLL multiplier */

PLL_ONLY) / 1000); /* Don't use the output from this PLL as the MCGOUT */

/* Check the value returned from pll_init() to make sure there wasn't an error */

if ((pll_1_clk_khz * 1000) < 0x100)

while(1);