Initialize TWR-MEM MMEM with Kinetis

terrybiberdorf — Thu, 07 Nov 2013 20:02:32 GMT

I'm having problems trying to initialize the MMEM on my TWR-MEM board.

I'm using the following init code:

#define MRAM_START_ADDRESS (*(volatile unsigned char*)(0x60000000))

void FlexBusInit()

{

SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK; // Enable the clock to the FlexBus

SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x0); //FlexBus Clock not divided

// Set the GPIO ports clocks

SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |

SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;

PORTB_PCR11 = PORT_PCR_MUX(5); // fb_ad[18]

PORTB_PCR16 = PORT_PCR_MUX(5); // fb_ad[17]

PORTB_PCR17 = PORT_PCR_MUX(5); // fb_ad[16]

PORTB_PCR18 = PORT_PCR_MUX(5); // fb_ad[15]

PORTC_PCR0 = PORT_PCR_MUX(5); // fb_ad[14]

PORTC_PCR1 = PORT_PCR_MUX(5); // fb_ad[13]

PORTC_PCR2 = PORT_PCR_MUX(5); // fb_ad[12]

PORTC_PCR4 = PORT_PCR_MUX(5); // fb_ad[11]

PORTC_PCR5 = PORT_PCR_MUX(5); // fb_ad[10]

PORTC_PCR6 = PORT_PCR_MUX(5); // fb_ad[9]

PORTC_PCR7 = PORT_PCR_MUX(5); // fb_ad[8]

PORTC_PCR8 = PORT_PCR_MUX(5); // fb_ad[7]

PORTC_PCR9 = PORT_PCR_MUX(5); // fb_ad[6]

PORTC_PCR10 = PORT_PCR_MUX(5); // fb_ad[5]

PORTD_PCR2 = PORT_PCR_MUX(5); // fb_ad[4]

PORTD_PCR3 = PORT_PCR_MUX(5); // fb_ad[3]

PORTD_PCR4 = PORT_PCR_MUX(5); // fb_ad[2]

PORTD_PCR5 = PORT_PCR_MUX(5); // fb_ad[1]

PORTD_PCR6 = PORT_PCR_MUX(5); // fb_ad[0]

PORTB_PCR20 = PORT_PCR_MUX(5); // fb_ad[31] used as d[7]

PORTB_PCR21 = PORT_PCR_MUX(5); // fb_ad[30] used as d[6]

PORTB_PCR22 = PORT_PCR_MUX(5); // fb_ad[29] used as d[5]

PORTB_PCR23 = PORT_PCR_MUX(5); // fb_ad[28] used as d[4]

PORTC_PCR12 = PORT_PCR_MUX(5); // fb_ad[27] used as d[3]

PORTC_PCR13 = PORT_PCR_MUX(5); // fb_ad[26] used as d[2]

PORTC_PCR14 = PORT_PCR_MUX(5); // fb_ad[25] used as d[1]

PORTC_PCR15 = PORT_PCR_MUX(5); // fb_ad[24] used as d[0]

PORTB_PCR19 = PORT_PCR_MUX(5); // fb_oe_b

PORTC_PCR11 = PORT_PCR_MUX(5); // fb_rw_b

PORTD_PCR1 = PORT_PCR_MUX(5); // fb_cs0_b

PORTD_PCR0 = PORT_PCR_MUX(5); // fb_ale

FB_CSAR0 = (unsigned int)&MRAM_START_ADDRESS; //Set Base address

FB_CSCR0 = ( (FB_CSCR_PS(1)) // 8-bit port

| (FB_CSCR_AA_MASK) // auto-acknowledge

| (FB_CSCR_WS(0x6)) ); // 2 wait states

FB_CSMR0 = ( (FB_CSMR_BAM(0x7)) //Set base address mask for 512K address space

| (FB_CSMR_V_MASK) ); //Enable cs valid signal

}

But after I complete this API call I found that I only have access to every other 16K block of data.

0x60000000 - 0x60001FFF -> work fine

0x60002000 - 0x60003FFF -> does not work

0x60004000 - 0x60005FFF -> work fine

0x60006000 - 0x60007FFF -> does not work

-------

0x6007C000 - 0x6007DFFF -> works fine

0x6007E000 - 0x6007FFFF -> does not work

Any suggestions?

Thanks

Re: Initialize TWR-MEM MMEM with Kinetis

terrybiberdorf — Thu, 07 Nov 2013 20:29:33 GMT

I forgot to add, I attempted this code on three tower configurations systems: TWR-K60N512, TWR-K60D100M and a TWR-K70F120M

Re: Initialize TWR-MEM MMEM with Kinetis

terrybiberdorf — Fri, 08 Nov 2013 21:26:19 GMT

After receiving a call from my Atmel FAE, the fix is to remove the J16 jumper.

Somehow the CPLD has corrupting the FlexBus communication.

Thanks Brad.

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Initialize TWR-MEM MMEM with Kinetis

Re: Initialize TWR-MEM MMEM with Kinetis

Re: Initialize TWR-MEM MMEM with Kinetis