Kinetis Microcontrollers中的主题 Re: KL05 clocking difficulty

KL05 clocking difficulty

mjbcswitzerland — Fri, 21 Feb 2014 00:15:05 GMT

Hi All

The KL05 doesn't have a PLL and I am trying, for the first time, to work with the FLL, whereby I would like to use the external 32.768kHz crystal as oscillator to generate 48MHz.

At the moment I can't explain the followig behaviour:

1. - Out of reset the FLL output is being used, which is seen by the rate that the SYSTICK is firing (around 21.05MHz). This is expected.

2. - If I configure MCG_C2 ready for the 32kHz crystal and clear the IREFS bit in MCG_C1 the crystal circuit starts to oscillate. OSCINIT is seen being set in MCG_S and the IREFST is cleared (meaning that the oscillator is ready and the source of the FLL is now the "external reference clock"). This seems good.

But, since the external crystal is more accurate than the internal reference clock I would have expected the FLL output to now be more accurate (32.768kHz x 640 = 20.97MHz) but there was no change in it (but maybe difficult to measure).

As a test, I short circuited the 32kHz crystal so that it was no longer supplying a clock but the SYSTICK continued to operate and I could also look at the registers with the debugger. I could step code and the MCG status still showed the same state - suggesting FEE mode (FLL engaged external) "In FEE, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock".

None of this is presently making sense. The MCG is confirming that it is using the external reference clock but this can't be the case because the processor still runs when this is physically removed. Since there was no operating frequency change it is quite certainly still using the FLL output, but derived from the internal 32kHz instead.

Furthermore, when attempting to move to any state not using the FLL output (CLKS not 0) the processor immediately "hangs"; debugger stops working.

Does anyone have an explanation as to what is actually going on??

Regards

Mmark

Re: KL05 clocking difficulty

apanecatl — Tue, 25 Feb 2014 20:43:16 GMT

If you want the FLL to provide a precise output frequency [32.768KHz * 732= 24MHz], you need to set the DMX32 bit field as [1], the FLL is fine tuned to work with 32.768KHz XTALs, if you leave the field as [0], the accuracy will drop; providing an output frequency in a range between 20MHz - 25MHz.

As for the "strange" phenomenon in which the FLL keeps providing a valid output, it is caused as a byproduct of the closed loop FLL circuitry, the feedback loop feeds a valid reference to the FLL input gate, the DCO then provides a valid output and so on; however when you try to switch the MCG mode the DCO loses its valid reference, thus leaving the core without a valid CLK signal to keep working.

Re: KL05 clocking difficulty

mjbcswitzerland — Thu, 27 Feb 2014 09:24:08 GMT

Thank you Pedro

The information about the FLL is useful. I have been working with the FLL operating at 48MHz (exactly from the 32kHz crystal) and found that stopping the oscillator (eg. short circuiting it) doesn't stop the FLL from operating but does sometimes change its frequences by up to 50%. This is no problem - just confusing originally since I thought that removing the clock would probably stop all activity.

What I have had no success with is moving to any other direct internal clock (rather than the FLL output) since any change to the clock configuration immediately stops anything working (processor hangs and debugger fails). Therefore I simply do the same as the reference code does -

- start the oscillator

- set a new FLL divide so that the clock ramps up from about 25MHz to 48MHz

There doesn't seem to be any problem with doing this although the user's manual suggests moving to a different configuration to allow the FLL to stabilise, which is what I originally wanted to do but found it failed.

Regards

Mark