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    <title>topic Using the on-chip cache on K70 with uClinux in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-the-on-chip-cache-on-K70-with-uClinux/m-p/162060#M692</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Kinetis K70 has two separate caches for the total of 16KB of the fast on-chip cache memory. This note explains how the caches are used in Emcraft's port of uClinux to the K70.&lt;BR /&gt;&lt;BR /&gt;First, to present the results first. With the cache enabled we get the following performance figures as tested on Emcraft's K70 System-On-Module (&lt;A href="http://www.emcraft.com/index.php/products/135" rel="nofollow" target="_blank"&gt;see this link for details&lt;/A&gt;). These tests run the K70 at 120Mhz:&lt;BR /&gt;&lt;BR /&gt;o) 112 BogoMIPS reported by the Linux kernel&lt;BR /&gt;&lt;BR /&gt;o) 108272 Dhrystones Per Second, which correspond to about ~44% of the result reported by dhrystone running under the MMU-full Linux on a 250Mhz PowerPC&lt;BR /&gt;&lt;BR /&gt;Here is some technical details.&lt;BR /&gt;&lt;BR /&gt;The K70 MCU has 2 separate caches:&lt;BR /&gt;&lt;BR /&gt;* Code bus cache, for addresses 0x00000000 through 0x1FFFFFFF.&lt;BR /&gt;* System bus cache, for addresses 0x20000000 through 0xFFFFFFFF.&lt;BR /&gt;&lt;BR /&gt;Each of the 2 caches is 8 KBytes is size: 8KB = (256 sets) * (16-byte lines) * (2-way set-associative)&lt;BR /&gt;&lt;BR /&gt;The cache essentially is the same memory as the built-in SRAM, from the physical memory perspective. Same access timings as for the built-in SRAM.&lt;BR /&gt;&lt;BR /&gt;When cache is enabled for the DRAM, data is transferred between the DRAM and cache in 16 bytes bursts.&lt;BR /&gt;&lt;BR /&gt;Emcraft's uClinux kernel makes use of both caches as follows:&lt;BR /&gt;&lt;BR /&gt;* Code bus cache enabled in Write-Through mode. This cache is used for the Linux kernel code.&lt;BR /&gt;* System bus cache enabled in Write-Back mode. This cache is used as the Linux run-time memory for allocation of dynamic buffers. An implication is that this cache is used both for dynamic kernel data and for user-space processes and loadable kernel modules.&lt;BR /&gt;&lt;BR /&gt;To implement the above architecture the kernel had to be modified to link its code in one address region (0x08000000) while making the kernel believe that its running from a different address region (0x70000000). This required modifications to the kernel linker scripts and also some changes to the core kernel code. The trade-off to this complexity is that both of the two caches are heavily used during the Linux operation resulting in optimal run-time performance.&lt;BR /&gt;&lt;BR /&gt;For those interested in detailed code, Emcraft's U-boot and Linux kernel trees are available at github.com.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 11 May 2012 18:39:28 GMT</pubDate>
    <dc:creator>vladimirkhusain</dc:creator>
    <dc:date>2012-05-11T18:39:28Z</dc:date>
    <item>
      <title>Using the on-chip cache on K70 with uClinux</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-the-on-chip-cache-on-K70-with-uClinux/m-p/162060#M692</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Kinetis K70 has two separate caches for the total of 16KB of the fast on-chip cache memory. This note explains how the caches are used in Emcraft's port of uClinux to the K70.&lt;BR /&gt;&lt;BR /&gt;First, to present the results first. With the cache enabled we get the following performance figures as tested on Emcraft's K70 System-On-Module (&lt;A href="http://www.emcraft.com/index.php/products/135" rel="nofollow" target="_blank"&gt;see this link for details&lt;/A&gt;). These tests run the K70 at 120Mhz:&lt;BR /&gt;&lt;BR /&gt;o) 112 BogoMIPS reported by the Linux kernel&lt;BR /&gt;&lt;BR /&gt;o) 108272 Dhrystones Per Second, which correspond to about ~44% of the result reported by dhrystone running under the MMU-full Linux on a 250Mhz PowerPC&lt;BR /&gt;&lt;BR /&gt;Here is some technical details.&lt;BR /&gt;&lt;BR /&gt;The K70 MCU has 2 separate caches:&lt;BR /&gt;&lt;BR /&gt;* Code bus cache, for addresses 0x00000000 through 0x1FFFFFFF.&lt;BR /&gt;* System bus cache, for addresses 0x20000000 through 0xFFFFFFFF.&lt;BR /&gt;&lt;BR /&gt;Each of the 2 caches is 8 KBytes is size: 8KB = (256 sets) * (16-byte lines) * (2-way set-associative)&lt;BR /&gt;&lt;BR /&gt;The cache essentially is the same memory as the built-in SRAM, from the physical memory perspective. Same access timings as for the built-in SRAM.&lt;BR /&gt;&lt;BR /&gt;When cache is enabled for the DRAM, data is transferred between the DRAM and cache in 16 bytes bursts.&lt;BR /&gt;&lt;BR /&gt;Emcraft's uClinux kernel makes use of both caches as follows:&lt;BR /&gt;&lt;BR /&gt;* Code bus cache enabled in Write-Through mode. This cache is used for the Linux kernel code.&lt;BR /&gt;* System bus cache enabled in Write-Back mode. This cache is used as the Linux run-time memory for allocation of dynamic buffers. An implication is that this cache is used both for dynamic kernel data and for user-space processes and loadable kernel modules.&lt;BR /&gt;&lt;BR /&gt;To implement the above architecture the kernel had to be modified to link its code in one address region (0x08000000) while making the kernel believe that its running from a different address region (0x70000000). This required modifications to the kernel linker scripts and also some changes to the core kernel code. The trade-off to this complexity is that both of the two caches are heavily used during the Linux operation resulting in optimal run-time performance.&lt;BR /&gt;&lt;BR /&gt;For those interested in detailed code, Emcraft's U-boot and Linux kernel trees are available at github.com.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 11 May 2012 18:39:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-the-on-chip-cache-on-K70-with-uClinux/m-p/162060#M692</guid>
      <dc:creator>vladimirkhusain</dc:creator>
      <dc:date>2012-05-11T18:39:28Z</dc:date>
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