<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: FTM CnV Update Problem in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266224#M68100</link>
    <description>If possible can you please explain the flow of how the PWM starts to generate please</description>
    <pubDate>Thu, 18 Dec 2025 14:42:52 GMT</pubDate>
    <dc:creator>Jana_muralidharan</dc:creator>
    <dc:date>2025-12-18T14:42:52Z</dc:date>
    <item>
      <title>FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2264552#M68094</link>
      <description>&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;So, I was trying to change the value of CnV based on the data's bit value&lt;/P&gt;&lt;P&gt;but the output stays in the initial wrote value but not changing&lt;/P&gt;&lt;P&gt;since I am just getting started in this MicroController MKE02Z64VLC4,&lt;/P&gt;&lt;P&gt;I don't know which step i am wrong, Please tell me which line is missing&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;LI-CODE lang="markup"&gt;#include "MKE02Z4.h"

#define FTM_MOD     24      // 25 ticks → 1.25us @ 20MHz
#define TICKS_0      7
#define TICKS_1     14

void FTM_Init(void)
{
    SIM-&amp;gt;SCGC |= SIM_SCGC_FTM2_MASK;

    FTM2-&amp;gt;MODE = FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK;

    FTM2-&amp;gt;CNTIN = 0;
    FTM2-&amp;gt;CNT   = 0;
    FTM2-&amp;gt;MOD   = FTM_MOD;

    FTM2-&amp;gt;CONTROLS[0].CnSC =
        FTM_CnSC_MSB_MASK |
        FTM_CnSC_ELSB_MASK;

    FTM2-&amp;gt;CONTROLS[0].CnV = TICKS_0;

    /* ENABLE CHANNEL OUTPUT (CRITICAL) */
    FTM2-&amp;gt;OUTMASK &amp;amp;= ~(1 &amp;lt;&amp;lt; 0);

    /* Initial load */
    *(volatile __UINT32_TYPE__ *)0x4003A098 = 0x0021;

    FTM2-&amp;gt;SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);

    *(volatile __UINT32_TYPE__ *)0x4003A064 = 0x00;
}

static inline void wait_ftm_period(void)
{
    while(!(FTM2-&amp;gt;SC &amp;amp; FTM_SC_TOF_MASK));
    FTM2-&amp;gt;SC &amp;amp;= ~FTM_SC_TOF_MASK;
}

uint32_t word = 0x5555;

int main(void)
{
    FTM_Init();

    while (1)
    {
        for(int i = 0; i &amp;lt; 16; i++)
        {
            if (word &amp;amp; (1UL &amp;lt;&amp;lt; i))
                *(volatile __UINT32_TYPE__ *)0x4003A010 = TICKS_1;
            else
            	*(volatile __UINT32_TYPE__ *)0x4003A010 = TICKS_0;

            /* ARM reload for next PWM cycle */
            *(volatile __UINT32_TYPE__ *)0x4003A098 = 0x0021;

            /* WAIT ONE PWM PERIOD */
            wait_ftm_period();
        }
    }
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 17 Dec 2025 08:20:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2264552#M68094</guid>
      <dc:creator>Jana_muralidharan</dc:creator>
      <dc:date>2025-12-17T08:20:06Z</dc:date>
    </item>
    <item>
      <title>Re: FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266056#M68098</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/258109"&gt;@Jana_muralidharan&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;When FTMEN = 1 (which you have already set), the main registers of the FTM (including CnV, MOD, CNTIN, etc.) are write-buffered; the actual registers are only updated when a synchronization/load event is triggered. Otherwise, the new values will remain in the buffer, and the channel will continue using the old initialized values. Please see the description in RM:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1766053059160.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370610i063A80731C689BF1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1766053059160.png" alt="Celeste_Liu_0-1766053059160.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_1-1766053104360.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370611i09D13549561BFEAD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_1-1766053104360.png" alt="Celeste_Liu_1-1766053104360.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_2-1766053261449.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370612i5478B9E90B975095/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_2-1766053261449.png" alt="Celeste_Liu_2-1766053261449.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Please modify the code below to set&amp;nbsp;LDOK=1 to enable the load:&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;            /* ARM reload for next PWM cycle */
            *(volatile __UINT32_TYPE__ *)0x4003A098 = 0x0201;//0x0200=LDOK, 0x0001=CH0SEL&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_3-1766053941711.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370614iF55EF724F5BB784D/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_3-1766053941711.png" alt="Celeste_Liu_3-1766053941711.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope it helps.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;------------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you!&lt;BR /&gt;------------------------------------------------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Thu, 18 Dec 2025 10:36:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266056#M68098</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2025-12-18T10:36:40Z</dc:date>
    </item>
    <item>
      <title>Re: FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266222#M68099</link>
      <description>&lt;P&gt;But isn't it be like this since in that register at the third byte from the left that is MSB has the LDOK not in the second right so it is the only possible thing&amp;nbsp; right&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;EM&gt;0x0020=LDOK, 0x0001=CH0SEL&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Isn't that right from my point of view I guess&lt;/P&gt;&lt;P&gt;And &lt;STRONG&gt;Thank you&lt;/STRONG&gt; &lt;STRONG&gt;for replying my post 🙇🏼‍&lt;LI-EMOJI id="lia_male-sign" title=":male_sign:"&gt;&lt;/LI-EMOJI&gt;&lt;/STRONG&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;And please clarify this doubt of mine too please..&lt;/P&gt;</description>
      <pubDate>Thu, 18 Dec 2025 14:41:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266222#M68099</guid>
      <dc:creator>Jana_muralidharan</dc:creator>
      <dc:date>2025-12-18T14:41:43Z</dc:date>
    </item>
    <item>
      <title>Re: FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266224#M68100</link>
      <description>If possible can you please explain the flow of how the PWM starts to generate please</description>
      <pubDate>Thu, 18 Dec 2025 14:42:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266224#M68100</guid>
      <dc:creator>Jana_muralidharan</dc:creator>
      <dc:date>2025-12-18T14:42:52Z</dc:date>
    </item>
    <item>
      <title>Re: FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266814#M68101</link>
      <description>&lt;P&gt;No, your understanding is wrong. I did a test, please see the result:&lt;BR /&gt;1) with the correct&amp;nbsp;&lt;STRONG&gt;&lt;EM&gt;0x02&lt;/EM&gt;&lt;/STRONG&gt;&lt;STRONG&gt;&lt;EM&gt;0&lt;/EM&gt;&lt;/STRONG&gt;&lt;STRONG style="font-family: inherit;"&gt;&lt;EM&gt;0=LDOK:&lt;BR /&gt;&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1766139388647.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370774iE84456B91C0DFE63/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1766139388647.png" alt="Celeste_Liu_0-1766139388647.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;2) with the wrong&amp;nbsp;&lt;STRONG&gt;&lt;EM&gt;0x0&lt;/EM&gt;&lt;/STRONG&gt;&lt;STRONG&gt;&lt;EM&gt;0&lt;/EM&gt;&lt;/STRONG&gt;&lt;STRONG style="font-family: inherit;"&gt;&lt;EM&gt;2&lt;/EM&gt;&lt;/STRONG&gt;&lt;STRONG style="font-family: inherit;"&gt;&lt;EM&gt;0=LDOK:&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_1-1766139442165.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370775i7B7C7FAA2146D27E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_1-1766139442165.png" alt="Celeste_Liu_1-1766139442165.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I’m afraid you’ve mixed up byte order and bit numbering. For a 32-bit register, the documentation refers to fields by bit (bit0 is the least significant, bit31 the most significant). LDOK = bit9 has nothing to do with which byte it’s in.&lt;/P&gt;
&lt;P&gt;Hope it helps.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;
&lt;P&gt;&lt;STRONG style="font-family: inherit;"&gt;&lt;EM&gt;&amp;nbsp;&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 19 Dec 2025 10:21:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266814#M68101</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2025-12-19T10:21:35Z</dc:date>
    </item>
    <item>
      <title>Re: FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266830#M68102</link>
      <description>&lt;P&gt;For this question, you can refer to our SDK demos for a deeper understanding.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://mcuxpresso.nxp.com/select" target="_blank"&gt;Select Board | MCUXpresso SDK Builder&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1766140071913.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370778iD85EE5D01A956C47/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1766140071913.png" alt="Celeste_Liu_0-1766140071913.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 19 Dec 2025 10:28:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266830#M68102</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2025-12-19T10:28:42Z</dc:date>
    </item>
    <item>
      <title>Re: FTM CnV Update Problem</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266962#M68104</link>
      <description>Thank you, For your answer. i was so dumb found. thank you very much&lt;BR /&gt;&lt;BR /&gt;but I used the built in library's mask but still the same issue but thanks any way for your imediate response</description>
      <pubDate>Fri, 19 Dec 2025 13:02:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM-CnV-Update-Problem/m-p/2266962#M68104</guid>
      <dc:creator>Jana_muralidharan</dc:creator>
      <dc:date>2025-12-19T13:02:34Z</dc:date>
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  </channel>
</rss>

