topic Re: Problems reading Data from an FPGA via Flexbus in Kinetis Microcontrollers

Problems reading Data from an FPGA via Flexbus

ChristofAbt — Wed, 26 Nov 2025 13:40:52 GMT

Good afternoon community, I try to read dta from an FPGA via the NXP Flexbus. The microcontroller is a MK66FN2M0VMD18. Address and Data are multiplexed on a 16bit bidirectional bus. The configuration is defined in FB_Device0_config. The definition can be seen in the attached file peripherals.c I included

wait states there but to no avail. The C-Code I want to read the data looks like that.

lsb_ad7779_u16 = *(volatile uint16_t*)(fb_base->CS[0].CSAR +129);

It is a read access to address 0d129 = 0x81.

I can observe the data inside the FPGA with an internal logic analyzer. The Address, data and

control signals are as expected for a flexbus read access. Unfortunately I do not see

the correct data in lsb_ad7779_u16.

The address and data is as expected even at the ports of the FPGA. I have no clue why the variable

does not contain the expected data.

Best regards in advance

Christof

Re: Problems reading Data from an FPGA via Flexbus

Pablo_Ramos — Wed, 26 Nov 2025 18:12:17 GMT

Hi @ChristofAbt,

I'm not able to see the peripherals.c file you mentioned.

Could you please share the configuration you are using for the FlexBus?

Best Regards,

Pablo

Re: Problems reading Data from an FPGA via Flexbus

ChristofAbt — Thu, 27 Nov 2025 06:54:14 GMT

Here is the flexbus configuration

* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

/* clang-format on */

flexbus_config_t FB_Device0_config = {

.chip = 0,

.chipBaseAddress = 0x60000000UL,

.chipBaseAddressMask = 0x0000U,

.byteEnableMode = false,

.autoAcknowledge = true,

.extendTransferAddress = false,

.byteLaneShift = kFLEXBUS_Shifted,

.portSize = kFLEXBUS_2Bytes,

.writeAddressHold = kFLEXBUS_Hold1Cycle,

.readAddressHold = kFLEXBUS_Hold1Or0Cycles,

.addressSetup = kFLEXBUS_FirstRisingEdge,

.waitStates = 0U,

.secondaryWaitStatesEnable = false,

.secondaryWaitStates = 0U,

.burstWrite = false,

.burstRead = false,

.writeProtect = false,

.group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE,

.group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4,

.group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5,

.group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST,

.group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA

};

Re: Problems reading Data from an FPGA via Flexbus

Pablo_Ramos — Wed, 03 Dec 2025 22:26:27 GMT

Hi @ChristofAbt,

Could you help me with the following questions?

When you mention that lsb_ad7779_u16 does not contain the expected data, what data does the variable currently hold?

How is the configuration of the pins being done?

Best Regards,

Pablo

Re: Problems reading Data from an FPGA via Flexbus

ChristofAbt — Mon, 08 Dec 2025 10:50:57 GMT

Hello Pablo,

the register contains random data. I can implement a kind of logic analyzer inside the FPGA and see correct data there. The flexbus pins are configured like that.

Best regards

Christof

Re: Problems reading Data from an FPGA via Flexbus

Pablo_Ramos — Mon, 08 Dec 2025 20:57:12 GMT

Hi @ChristofAbt,

Thanks for sharing the settings.

When you mention that the register contains random data, does it change with every execution?

Are you able to read the bus using an oscilloscope or a logic analyzer? This would help verify the integrity of the data across the bus.

Best Regards,
Pablo