CPU not Halted when jlink segger debug is used

RohitKewatLFT — Thu, 26 Dec 2024 14:21:40 GMT

Hi All ,

I am not able to flash my hex file in to MK10DN512VLK10 using J Link segger , when try to flash I am geting error like CPU not halted , please find below log:

SDK version : 2.2.0
MCUXpresso IDE v11.10.0

Executing flash operation 'Program' (Program executable into flash TEST_MK10D10_Project.axf) - Fri Dec 20 17:31:10 IST 2024
Checking MCU info...
Scanning for targets...
Executing flash action...
SEGGER J-Link Commander V7.96o (Compiled Jun 26 2024 16:18:16)
DLL version V7.96o, compiled Jun 26 2024 16:17:29
J-Link Command File read successfully.
Processing script file...
J-Link>ExitOnError 1
J-Link Commander will now exit on Error
J-Link>r
J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: J-Link V12 compiled Jul 3 2024 16:56:02
Hardware version: V12.00
J-Link uptime (since boot): 0d 00h 01m 33s
S/N: 52008676
License(s): GDB
USB speed mode: High speed (480 MBit/s)
VTref=3.354V
Target connection not established yet but required for command.
Device "MK10DN512XXX10" selected.
Connecting to target via JTAG
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 16us
InitTarget() start
InitTarget()
JTAG selected. Identifying JTAG Chain...
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
JTAG Chain Identified. Connecting to DAP TAP...
Successfully connected to selected DAP TAP.
Timeout while halting CPU.
InitTarget() end - Took 360ms
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
DPv0 detected
Scanning AP map to find all available APs
AP[2]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
AP[1]: JTAG-AP (IDR: 0x001C0000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105E00D PID 000BB000 SCS
[0][1]: E0001000 CID B105E00D PID 003BB002 DWT
[0][2]: E0002000 CID B105E00D PID 002BB003 FPB
[0][3]: E0000000 CID B105E00D PID 003BB001 ITM
[0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU
[0][5]: E0041000 CID B105900D PID 000BB925 ETM
[0][6]: E0042000 CID B105900D PID 003BB907 ETB
[0][7]: E0043000 CID B105900D PID 001BB908 CSTF
Memory zones:
"Default" Description: Default access mode
Cortex-M4 identified.
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
CPU could not be halted
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
CPU could not be halted
AfterResetTarget() start
AfterResetTarget()
_TargetHalt: CPU did not halt.
AfterResetTarget() end - Took 205ms
CPU could not be halted
****** Error: Failed to halt CPU.
J-Link>h
CPU could not be halted
J-Link>loadfile "C:\Users\Rok\Documents\MCUXpressoIDE_11.10.0_3148\workspace_MK10\TEST_MK10D10_Project\Debug\TEST_MK10D10_Project.hex"
'loadfile': Performing implicit reset & halt of MCU.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
CPU could not be halted
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
CPU could not be halted
AfterResetTarget() start
AfterResetTarget()
_TargetHalt: CPU did not halt.
AfterResetTarget() end - Took 204ms
CPU could not be halted
****** Error: Failed to halt CPU.
CPU could not be halted
Downloading file [C:\Users\Rohit.Kewat\Documents\MCUXpressoIDE_11.10.0_3148\workspace_MK10\TEST_MK10D10_Project\Debug\TEST_MK10D10_Project.hex]...
CPU could not be halted
****** Error: Verification of RAMCode failed @ address 0x1FFF0000.
Write: 0xA801BE00 F0009900
0x00000000 00000000
Failed to prepare for programming.
Failed to download RAMCode!
Cannot read register 16 (XPSR) while CPU is running
Cannot read register 20 (CFBP) while CPU is running
Cannot read register 0 (R0) while CPU is running
Cannot read register 1 (R1) while CPU is running
Cannot read register 2 (R2) while CPU is running
Cannot read register 3 (R3) while CPU is running
Cannot read register 4 (R4) while CPU is running
Cannot read register 5 (R5) while CPU is running
Cannot read register 6 (R6) while CPU is running
Cannot read register 7 (R7) while CPU is running
Cannot read register 8 (R8) while CPU is running
Cannot read register 9 (R9) while CPU is running
Cannot read register 10 (R10) while CPU is running
Cannot read register 11 (R11) while CPU is running
Cannot read register 12 (R12) while CPU is running
Cannot read register 14 (R14) while CPU is running
Cannot read register 15 (R15) while CPU is running
Canno
Unspecified error -1
Script processing completed.
Unable to perform operation!
Command failed with exit code 1

Re: CPU not Halted when jlink segger debug is used

Celeste_Liu — Mon, 30 Dec 2024 04:10:20 GMT

Hello @RohitKewatLFT ,

Thanks for your post. I'm very sorry for the late reply. It appears that you are using the programming tool integrated within MCUXpresso. What about JFlash? Does the same problem occur when using it? Besides, are there any abnormal pop-up windows?
You are currently using JTAG. What will happen if you switch to SWD? You might as well give it a try and let me know the result. This will assist us in locating and resolving the problem more accurately.

BRs,

Celeste

topic Re: CPU not Halted when jlink segger debug is used in Kinetis Microcontrollers

CPU not Halted when jlink segger debug is used

Re: CPU not Halted when jlink segger debug is used