<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Kinetis MicrocontrollersのトピックJTAG Chaining K10 with Xilinx Ultrascale FPGA</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1846474#M66290</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are designing a VPX SBC board in which we are using K10 as IPMC. Now we have Xilinx FPGA also on the board.&lt;/P&gt;&lt;P&gt;Now, as per VPX standard connector, there is only one port of JTAG available on P0 connector.&lt;/P&gt;&lt;P&gt;So, we are planning to include Xilinx FPGA and K10 microcontroller in a single JTAG chain.&lt;/P&gt;&lt;P&gt;As, per Xilinx, Vivado can identify third part devices but need to import a csv file in Vivado which includes details like ID code etc:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;My questions here are:&lt;/P&gt;&lt;P&gt;1. Does K10 IDE supports third party devices in the JTAG chain?&lt;/P&gt;&lt;P&gt;2. Please share the properties required for detecting K10 in Xilinx Vivado IDE like&amp;nbsp;&lt;/P&gt;&lt;TABLE border="0" width="256" cellspacing="0" cellpadding="0"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="64" height="19"&gt;idcode&lt;/TD&gt;&lt;TD width="64"&gt;mask&lt;/TD&gt;&lt;TD width="64"&gt;irlen&lt;/TD&gt;&lt;TD width="64"&gt;name&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am attaching the example csv file required by Xilinx.&lt;/P&gt;&lt;P&gt;An early response will be highly appreciated.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Lalit&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sat, 13 Apr 2024 11:12:25 GMT</pubDate>
    <dc:creator>lalit_verma</dc:creator>
    <dc:date>2024-04-13T11:12:25Z</dc:date>
    <item>
      <title>JTAG Chaining K10 with Xilinx Ultrascale FPGA</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1846474#M66290</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are designing a VPX SBC board in which we are using K10 as IPMC. Now we have Xilinx FPGA also on the board.&lt;/P&gt;&lt;P&gt;Now, as per VPX standard connector, there is only one port of JTAG available on P0 connector.&lt;/P&gt;&lt;P&gt;So, we are planning to include Xilinx FPGA and K10 microcontroller in a single JTAG chain.&lt;/P&gt;&lt;P&gt;As, per Xilinx, Vivado can identify third part devices but need to import a csv file in Vivado which includes details like ID code etc:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;My questions here are:&lt;/P&gt;&lt;P&gt;1. Does K10 IDE supports third party devices in the JTAG chain?&lt;/P&gt;&lt;P&gt;2. Please share the properties required for detecting K10 in Xilinx Vivado IDE like&amp;nbsp;&lt;/P&gt;&lt;TABLE border="0" width="256" cellspacing="0" cellpadding="0"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="64" height="19"&gt;idcode&lt;/TD&gt;&lt;TD width="64"&gt;mask&lt;/TD&gt;&lt;TD width="64"&gt;irlen&lt;/TD&gt;&lt;TD width="64"&gt;name&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am attaching the example csv file required by Xilinx.&lt;/P&gt;&lt;P&gt;An early response will be highly appreciated.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Lalit&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 13 Apr 2024 11:12:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1846474#M66290</guid>
      <dc:creator>lalit_verma</dc:creator>
      <dc:date>2024-04-13T11:12:25Z</dc:date>
    </item>
    <item>
      <title>Re: JTAG Chaining K10 with Xilinx Ultrascale FPGA</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1848025#M66304</link>
      <description>&lt;P&gt;Hi NXP team,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any response on this will he very helpful for us.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Lalit&lt;/P&gt;</description>
      <pubDate>Tue, 16 Apr 2024 10:17:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1848025#M66304</guid>
      <dc:creator>lalit_verma</dc:creator>
      <dc:date>2024-04-16T10:17:14Z</dc:date>
    </item>
    <item>
      <title>Re: JTAG Chaining K10 with Xilinx Ultrascale FPGA</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1848811#M66307</link>
      <description>&lt;P&gt;Hi, Lalit,&lt;/P&gt;
&lt;P&gt;I suggest you use dedicated JTAG connector for both K10 and FPGA.&lt;/P&gt;
&lt;P&gt;The JTAG chain requires IDE tools support for example Keil, MCUXPresso or IAR and the probe device support like Segger J-Link device, it is difficult.&lt;/P&gt;
&lt;P&gt;Hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
      <pubDate>Wed, 17 Apr 2024 07:43:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1848811#M66307</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2024-04-17T07:43:55Z</dc:date>
    </item>
    <item>
      <title>Re: JTAG Chaining K10 with Xilinx Ultrascale FPGA</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1848942#M66308</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;XiangJun Rong,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I can see that NXP supports PEmicro Multilink debuuger for K10.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Please find below the link which describes how we can do JTAG daisy chaining using Multilink with different devices like K10 MCU, FPGA etc:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.pemicro.com/blog/index.cfm?post_id=136" target="_blank"&gt;https://www.pemicro.com/blog/index.cfm?post_id=136&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Now, if there is an option for enabling JTAG daisy chaining in&amp;nbsp;MCUXPresso, it will be really helpful for us.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Please let me know how to enable JTAG daisy chaining in MCUXPresso.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Lalit&lt;/P&gt;</description>
      <pubDate>Wed, 17 Apr 2024 09:54:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1848942#M66308</guid>
      <dc:creator>lalit_verma</dc:creator>
      <dc:date>2024-04-17T09:54:57Z</dc:date>
    </item>
    <item>
      <title>Re: JTAG Chaining K10 with Xilinx Ultrascale FPGA</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1849446#M66312</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;As you pointed out that the probe devices such as J-Link and Multilink Universal support the JTAG daisy chain function, but the IDE such as MCUXPresso tools does not support the jtag daisy chain function.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
      <pubDate>Thu, 18 Apr 2024 02:57:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/JTAG-Chaining-K10-with-Xilinx-Ultrascale-FPGA/m-p/1849446#M66312</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2024-04-18T02:57:58Z</dc:date>
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  </channel>
</rss>

