topic Re: Set MCGOUTCLK as 120 Mhz in Kinetis Microcontrollers

Set MCGOUTCLK as 120 Mhz

Devyy — Tue, 09 Jan 2024 13:10:34 GMT

Hello everyone !

I'm asking your help today to configure the MCG module of my Kinetis KV58xxx.
I'm trying to set the MCGOUTCLK at 120 MHz. At reset it's set at 21 Mhz.

I'm using the board TWR-KV58220M with a crystal (external clock ?) at 8 MHz.

The reference manual of the mcu gives an example of how to do it from an external clock equal to 16 Mhz. (32.6.3.1 page 708).

I followed the steps and lauched my program. Every registers changes works but after the last line, my code crashes.

So, I tried to debug it and this is how I found that my crystal was 8 MHz and not 16 MHz.
I changed the first line of the code (from 0x2C to 0x1C) to enter the correct range but it's still not working.

I dont exactly understand how the clock distribution works and still learning. That's why i'm not using pre-made functions. I'm modifying every registers without functions.

Thank you in advance for your help,

Devyy

Re: Set MCGOUTCLK as 120 Mhz

xiangjun_rong — Wed, 10 Jan 2024 08:26:12 GMT

Hi,

The TWR-KV58220M board embeds the 50MHz clock source, so you can use the 50MHz clock source to get high clock frequency based on PLL.

After Reset, the default is FBI mode, following up a state machine, we can get PEE mode.

The SDK package provides the api function to get high clock frequency with PEE mode.

I post the functions, you can call BOARD_BootClockRUN() to get 150MHz core clock frequency.

If you do want to write the MCG register to be familiar with the clock module, pls update the ticket.

Hope it can help you

XiangJun Rong

const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
 .drs = kMCG_DrsHigh, /* High frequency range */
 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
 .pll0Config =
 {
 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
 .vdiv = 0x8U, /* VCO divider: multiplied by 24 */
 },
};
const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
 .er32ksrc=SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
 .clkdiv1 = 0x01150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
};
const osc_config_t oscConfig_BOARD_BootClockRUN = {
 .freq = 50000000U, /* Oscillator frequency: 48000000Hz */
 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
 .workMode = kOSC_ModeExt, /* Use external clock */
 .oscerConfig = {
 .enableMode =
kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
 }};
 
/*******************************************************************************
 * Code for BOARD_BootClockRUN configuration
 ******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
 CLOCK_CONFIG_SetSimSafeDivs();
/* Initializes OSC0 according to board configuration. */
 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
/* Configure FLL external reference divider (FRDIV). */
 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
/* Set MCG to PEE mode. */
 CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockRUN.pll0Config);
/* Configure the Internal Reference clock (MCGIRCLK). */
 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
 mcgConfig_BOARD_BootClockRUN.fcrdiv);
/* Set the clock configuration in SIM module. */
 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
 

Re: Set MCGOUTCLK as 120 Mhz

Devyy — Wed, 10 Jan 2024 08:54:46 GMT

Hey, first of all thank you for your answer.

Honestly I already had that function, but I would like to manually configure MCG registers.

Additionally I have a question, you're saying that the defaut mode is FBI, isnt the default mode FEI ?
The documentation says that to reach PEE mode from reset, I have to go through FEI (reset mode) -> FBE -> PBE -> PEE.

Thank

Re: Set MCGOUTCLK as 120 Mhz

xiangjun_rong — Wed, 10 Jan 2024 09:35:40 GMT

Hi,
I am sorry, this is typo, after Reset, the default mode is FEI instead of FBI.

Pls refer to the clock configuration attached in similar register writing.

XiangJun Rong

Re: Set MCGOUTCLK as 120 Mhz

Devyy — Mon, 15 Jan 2024 10:58:52 GMT

The problem is finally solved.

The main problem came from the primary frequency.

The crystal on the TWRKV58F220M delivers a frequency of 24 MHz and not 8 Mhz, thats why it didn't worked, my calculations were not correct.

Now it works, perfectly.

Thank you