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    <title>Kinetis MicrocontrollersのトピックRe: RAM Testing in S9KEAZ128</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1776001#M65802</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;The S9KEAZ128 has 16KB SRAM, which ranges from 0x1FFF_E000 to 0x2000_1FFF, the 16KB/4=4K, which is 0x1000 or 2048&lt;/P&gt;
&lt;P&gt;So pls try to modify:&lt;/P&gt;
&lt;P&gt;ldr r2, =0x1fffe000 /* Base address to start */&lt;/P&gt;
&lt;P&gt;otherwise, the high address will be incorrect.&lt;/P&gt;
&lt;P&gt;Secondly, pls check the stack in the linker file, I suppose you'd better not write/read the stack.&lt;/P&gt;
&lt;P&gt;Hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
    <pubDate>Mon, 18 Dec 2023 03:57:10 GMT</pubDate>
    <dc:creator>xiangjun_rong</dc:creator>
    <dc:date>2023-12-18T03:57:10Z</dc:date>
    <item>
      <title>RAM Testing in S9KEAZ128</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1774473#M65783</link>
      <description>&lt;P&gt;Hi, i am doing RAM Test (SRAM -16kb)on the startup code before RAM Configuration and after the Reset Handler, while i write and read the entire RAM region i face the below issues,&lt;/P&gt;&lt;P&gt;1. it shows&amp;nbsp;&lt;SPAN&gt;PE-ERROR: Warning. Can't read memory while part is running. @200004e8 (4 bytes)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2. No source available for "(gdb[2].proc[42000].threadGroup[i1],gdb[2].proc[42000].OSthread[1]).thread[1].frame[0]"&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3.it will get inside the Reset Handler while running and &lt;SPAN class=""&gt;LR and SP register Updating with the reference value which i give&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Below is the code which i tried for RAM Testing&lt;/P&gt;&lt;DIV&gt;&lt;STRONG&gt;b ram_test_1&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&amp;nbsp;error:&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr r5, =0x20002ff0&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr r6, =0xaaff&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r6, [r5]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;b ram_config&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;ram_test_1:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r2, =0x1ffff000 /* Base address to start */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r1, =0 /* Counter to keep track of address during write operation */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r3, =2048&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;STRONG&gt;loop_1:&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0xaaaaaaaa&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr r7, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0x55555555&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r7, [r2]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r2, #4 /* increments the address by 4 bytes */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r1, #1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r1, r3&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; blt loop_1 /*if r2 less than 0x200003f0 Branch less than - BLT the loop continues */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r5, =0x20002ff0&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr r6, =0xaa55&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r6, [r5]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;P&gt;ram_config:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kindly clarify.&lt;/P&gt;</description>
      <pubDate>Thu, 14 Dec 2023 06:47:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1774473#M65783</guid>
      <dc:creator>logapriya</dc:creator>
      <dc:date>2023-12-14T06:47:49Z</dc:date>
    </item>
    <item>
      <title>Re: RAM Testing in S9KEAZ128</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1776001#M65802</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;The S9KEAZ128 has 16KB SRAM, which ranges from 0x1FFF_E000 to 0x2000_1FFF, the 16KB/4=4K, which is 0x1000 or 2048&lt;/P&gt;
&lt;P&gt;So pls try to modify:&lt;/P&gt;
&lt;P&gt;ldr r2, =0x1fffe000 /* Base address to start */&lt;/P&gt;
&lt;P&gt;otherwise, the high address will be incorrect.&lt;/P&gt;
&lt;P&gt;Secondly, pls check the stack in the linker file, I suppose you'd better not write/read the stack.&lt;/P&gt;
&lt;P&gt;Hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
      <pubDate>Mon, 18 Dec 2023 03:57:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1776001#M65802</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2023-12-18T03:57:10Z</dc:date>
    </item>
    <item>
      <title>Re: RAM Testing in S9KEAZ128</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1777953#M65820</link>
      <description>&lt;P&gt;/* Specify the memory areas RAM 16 Kb */&lt;BR /&gt;MEMORY&lt;BR /&gt;{&lt;BR /&gt;SRAM : ORIGIN = 0x1FFFF000, LENGTH = 0x00004000&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;1. this is our RAM region which is specified in the linker file so i used the 0x1ffff000 as base address&lt;/P&gt;&lt;P&gt;2. As you mentioned i didn't write the stack area but still i face the previous warnings and it doesn't get into main function ,here is the modified code&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;ram_test_3:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r2, =__HeapBase /* Base address to start Heap segment 0x1ffff494*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r1, =0 /* Counter to keep track of address during write operation */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r3, =320 /*Size of data segment 0x500 = 1280 bytes /4(each adress having 4 bytes) = 320 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;loop_3:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0xaaaaaaaa&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr r7, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0x55555555&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r7, [r2]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r2, #4 /* increments the address by 4 bytes */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r1, #1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r1, r3&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; blt loop_3 /*if r2 less than 0x200003f0 Branch less than - BLT the loop continues */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;ram_test_2:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r2, =__bss_start__ /* Base address to start bss segment 0x1ffff494*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r1, =0 /* Counter to keep track of address during write operation */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r3, =496 /*Size of data segment 0x7c0 = 1984 bytes/4 = 496 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;loop_2:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0xaaaaaaaa&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr r7, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0x55555555&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r7, [r2]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r2, #4 /* increments the address by 4 bytes */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r1, #1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r1, r3&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; blt loop_2 /*if r2 less than 0x200003f0 Branch less than - BLT the loop continues */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;ram_test_1:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r2, =__data_start__ /* Base address to start data segment 0x1ffff000*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r1, =0 /* Counter to keep track of address during write operation */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r3, =293 /*Size of data segment 0x494 = 1172bytes / 4 = 293 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;loop_1:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0xaaaaaaaa&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr r7, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0x55555555&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r7, [r2]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r2, #4 /* increments the address by 4 bytes */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r1, #1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r1, r3&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; blt loop_1 /*if r2 less than 0x200003f0 Branch less than - BLT the loop continues */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;ram_test_4:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r2, =0x2000500 /* Base address to start Remaining segments 0x200000f0*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r1, =0 /* Counter to keep track of address during write operation */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ldr&amp;nbsp; &amp;nbsp; r3, =2745 /*Size of Remaining segment 10,980 bytes/4(each adress having 4 bytes) */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;loop_4:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0xaaaaaaaa&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ldr r7, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr&amp;nbsp; &amp;nbsp; r0, =0x55555555&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; str r0, [r2] /* Copy the values into register */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; ldr r4, [r2]&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r4, r0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bne error&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;str r7, [r2]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r2, #4 /* increments the address by 4 bytes */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adds r1, #1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; cmp r1, r3&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; blt loop_4 /*if r2 less than 0x200003f0 Branch less than - BLT the loop continues */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;3. Is there any ways to over come the warnings mentioned?&lt;/P&gt;&lt;P&gt;4. Is it possible to read write the entire SRAM region, except Stack in the startup code for testing purpose ?&lt;/P&gt;&lt;P&gt;5.I want to know what is the process happening in the SRAM before startup code execution.&lt;/P&gt;&lt;P&gt;kindly clarify&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 20 Dec 2023 12:02:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1777953#M65820</guid>
      <dc:creator>logapriya</dc:creator>
      <dc:date>2023-12-20T12:02:00Z</dc:date>
    </item>
    <item>
      <title>Re: RAM Testing in S9KEAZ128</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1777980#M65821</link>
      <description>Part address issues aside, take a look at this RAM Test:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://www.ganssle.com/testingram.htm" target="_blank"&gt;http://www.ganssle.com/testingram.htm&lt;/A&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 20 Dec 2023 13:01:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/RAM-Testing-in-S9KEAZ128/m-p/1777980#M65821</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2023-12-20T13:01:20Z</dc:date>
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