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    <title>Kinetis MicrocontrollersのトピックMKE02 FLL Recommended Input Frequency Range</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKE02-FLL-Recommended-Input-Frequency-Range/m-p/1726268#M65554</link>
    <description>&lt;P&gt;Hi NXP Team&lt;/P&gt;&lt;P&gt;I am using Kinetis KE02 family microcontroller MKE02Z64VLD4 with external crystal oscillator 7.3728MHz as I need to generate serial port baud rate of 460800.&lt;/P&gt;&lt;P&gt;I have set the FLL with external crystal in FEE Engaged External Mode, with:&lt;/P&gt;&lt;P&gt;7.3728MHz divide by 256 = 28.8 KHz. This 28.8 KHz is fed to FLL, which then outputs&lt;/P&gt;&lt;P&gt;28.8 KHz * 1024 = 29.4912MHz (and BUS CLOCK at divide by 2 = 14.7456 MHz)&lt;/P&gt;&lt;P&gt;BUT&lt;/P&gt;&lt;P&gt;As per data sheet of MKE02, the FLL is optimized for 32-40 MHz output frequency range.&lt;/P&gt;&lt;P&gt;Input of FLL is recommended to be in the range of 31.25 KHz to 39.0625 KHz&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;What does it actually means?&lt;/P&gt;&lt;P&gt;Can I use FLL using 7.3728MHz external crystal and get a core frequency of 29.4912MHz?&lt;/P&gt;&lt;P&gt;Will FLL maintain the LOCK for this frequency (29.4912MHz)?&lt;/P&gt;&lt;P&gt;Or I cannot use the above scheme, as 28.8 KHz is lower than the recommended minimum of 31.25 KHz.&lt;/P&gt;</description>
    <pubDate>Wed, 20 Sep 2023 11:01:09 GMT</pubDate>
    <dc:creator>ad_sabir86</dc:creator>
    <dc:date>2023-09-20T11:01:09Z</dc:date>
    <item>
      <title>MKE02 FLL Recommended Input Frequency Range</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKE02-FLL-Recommended-Input-Frequency-Range/m-p/1726268#M65554</link>
      <description>&lt;P&gt;Hi NXP Team&lt;/P&gt;&lt;P&gt;I am using Kinetis KE02 family microcontroller MKE02Z64VLD4 with external crystal oscillator 7.3728MHz as I need to generate serial port baud rate of 460800.&lt;/P&gt;&lt;P&gt;I have set the FLL with external crystal in FEE Engaged External Mode, with:&lt;/P&gt;&lt;P&gt;7.3728MHz divide by 256 = 28.8 KHz. This 28.8 KHz is fed to FLL, which then outputs&lt;/P&gt;&lt;P&gt;28.8 KHz * 1024 = 29.4912MHz (and BUS CLOCK at divide by 2 = 14.7456 MHz)&lt;/P&gt;&lt;P&gt;BUT&lt;/P&gt;&lt;P&gt;As per data sheet of MKE02, the FLL is optimized for 32-40 MHz output frequency range.&lt;/P&gt;&lt;P&gt;Input of FLL is recommended to be in the range of 31.25 KHz to 39.0625 KHz&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;What does it actually means?&lt;/P&gt;&lt;P&gt;Can I use FLL using 7.3728MHz external crystal and get a core frequency of 29.4912MHz?&lt;/P&gt;&lt;P&gt;Will FLL maintain the LOCK for this frequency (29.4912MHz)?&lt;/P&gt;&lt;P&gt;Or I cannot use the above scheme, as 28.8 KHz is lower than the recommended minimum of 31.25 KHz.&lt;/P&gt;</description>
      <pubDate>Wed, 20 Sep 2023 11:01:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKE02-FLL-Recommended-Input-Frequency-Range/m-p/1726268#M65554</guid>
      <dc:creator>ad_sabir86</dc:creator>
      <dc:date>2023-09-20T11:01:09Z</dc:date>
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