topic Re: LPSPI + DMA Buffer start from 4th index for slave device in Kinetis Microcontrollers

LPSPI + DMA Buffer start from 4th index for slave device

Sridharanblr — Mon, 26 Dec 2022 05:11:26 GMT

Hi ,

We are using the MKE15Z256xxx7 controller for transfer and receive the data through SPI with DMA for Pmod-sf3 flash( Customized SPI driver) . The communication is fine, Read/Write too is also fine, however the data is read from index 4 instead of 0th index, ie first we need this data to be from 1st index.

E.g : Current working of code

Write command : Buffer status

WriteBuff[10u] = {0x02, 0x00, 0xff, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06};
ReadBuff[10u] = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};

Read Command: Buffer status

WriteBuff[10u] = {0x03, 0x00, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
ReadBuff[10u] = {0xff, 0xff, 0xff, 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06};

Expected: Read command: Should read from index 0.

WriteBuff[10u] = {0x03, 0x00, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
ReadBuff[6u] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06};

Here we are using a single buffer which contain Command + Address + Data, We are using same buffer for writing and while reading too.

Query :

1. We wanted the data to be read from 0th index.

2. Can we have a sample code SDK (SPI + DMA) which uses separate buffer for command/Address and read/write.

3. How can we not trigger the interrupt for first 4bytes( Command+Adress) and then trigger SPI interrupt so that it read from 0th index.

Re: LPSPI + DMA Buffer start from 4th index for slave device

RaRo — Wed, 28 Dec 2022 20:53:01 GMT

Hello @Sridharanblr,

Just for double check, could you please try out the MKE15Z256 SDK examples: frdm15z_lpspi_3wire_edma_transfer_master and frdm15z_lpspi_edma_b2b_transfer_master?

Are you seeing the same issue with the examples?

Regards, Raul.

Re: LPSPI + DMA Buffer start from 4th index for slave device

Sridharanblr — Thu, 29 Dec 2022 06:57:40 GMT

Hi @RaRo

Yes, we did same changes in SDK we found same behaviors, The read data is from 4th index.

Below changes was reworked on SDK :

Master : NXP FRDM HW

Slave : PMOD SF3

Write command/Address/Data(250) : 0x2, 0x00, 0xff,0x00, xx,xxx,xxx........upto 250byte

Read command/Address/Data(250) : 0x3, 0x00, 0xff,0x00, Data reading starts from here ie 4th index.

Regards

Sridharan

Re: LPSPI + DMA Buffer start from 4th index for slave device

RaRo — Thu, 29 Dec 2022 17:51:28 GMT

Hello @Sridharanblr,

Could you please try out with other examples that don't include eDMA? For example, lpspi_interrupt_b2b_transfer_master and/or lpspi_polling_b2b_transfer_master. This way we could see if it is something to do with the eDMA and how it handles the data and the buffer.

Also, could you please attach the signal behavior with a logic analyzer of the transfer?

Regards, Raul.

Re: LPSPI + DMA Buffer start from 4th index for slave device

madhavaishriram — Fri, 30 Dec 2022 05:20:20 GMT

Hi @RaRo

Please find the attached snap for without DMA transmission with PMOD-SF3 and the logic analyzer data.

We have seen same issue.

Regards,

Shriram Madhavai

Re: LPSPI + DMA Buffer start from 4th index for slave device

Sridharanblr — Mon, 02 Jan 2023 06:06:35 GMT

Hi Raul,

the above screenshot and our reply is based on MKE15Z256 SDK frdm15z_lpspi_edma_b2b_transfer_master.

jfi: Without DMA we first written the Command and address to TDR register and then we enabled SPI interrupt, by this way the read/Write was exactly happing for 1st index location of the buffer.

Re: LPSPI + DMA Buffer start from 4th index for slave device

RaRo — Wed, 04 Jan 2023 20:55:17 GMT

Hello @Sridharanblr,

Just for double check could you please confirm if the signal screen shot was using eDMA?

Also, could you try writing the Command (0x03) + address (0x00 0xFF 0x00) to TDR register before enabling the EDMA_EnableChannelInterrupts, to see if you can replicate the reading/writing in 1st index in SPI with the eDMA?

Best regards, Raul.

Re: LPSPI + DMA Buffer start from 4th index for slave device

madhavaishriram — Fri, 06 Jan 2023 06:19:32 GMT

Hi @RaRo

We have tested with by writing Cmd 0x03 and Address 0x00, 0xff, 0x00 in to TDR register.

but getting same issue after that too.

Please find the code before read.

Below is the code to writing into TDR register directly.

The snap after read by calling read api.

Please see the log after read.

Re: LPSPI + DMA Buffer start from 4th index for slave device

RaRo — Mon, 09 Jan 2023 19:27:41 GMT

Hello @madhavaishriram,

Could you please check if this behavior still happens using the LPSPI+eDMA communication with another device?

Regards, Raul.

Re: LPSPI + DMA Buffer start from 4th index for slave device

madhavaishriram — Mon, 16 Jan 2023 04:34:49 GMT

HI @RaRo

We have PMOD-SF3 as slave device and tested on same device and getting same behavior with and w/o dma. So please check at your end and reply with solutions,

Thanks and Regards,

Shriram Madhavai

Re: LPSPI + DMA Buffer start from 4th index for slave device

RaRo — Mon, 16 Jan 2023 20:02:07 GMT

Hello @madhavaishriram,

Unfortunately, we don't have a PMOD-SF3 flash to replicate your issue. We recommended you the example code, because the reading of data should work from the first index.

As a suggestion, you could try reading/entering another direction of the flash.

Also, looking at 3V, 256Mb: Multiple I/O Serial Flash Memory PMOD-SF3 datasheet (Command Definitions [Table 18. Command Set]), for writing/programming data in the flash you first need to enable the writing; just for double check, you could confirm if you are enabling the writing first before programming the data to the flash and disabling it before reading the data [WRITE Operations].

Finally, you could try using only SPI first to see if everything it is working fine, before trying out with DMA.

Best regards, Raul.