Best practice for K8x QSPI Dual-Quad Address Ranges

deniscollis — Fri, 19 Aug 2022 20:00:28 GMT

Though I'd share...

The K8x QSPI peripheral can accept one or two QSPI flash devices, or a dual-die device (which is really only two identical flash dies and one chip). Each can have a maximum size of 64MB.

In some NXP K8x QSPI peripheral examples the second die address range starts where the first ends. So for example:

2x 32MB dies would have:
Bank-A: 0x68000000-0x69FFFFFF
Bank-B: 0x6A000000-0x6BFFFFFF

and 2x 16MB dies would have:
Bank-A: 0x68000000-0x68FFFFFF
Bank-B: 0x69000000-0x69FFFFFF

This arrangement is no longer ideal with the latest Segger Flasher-ARM/J-Flash.

In earlier J-Flash versions (many moons ago) I recall the ability to change these addresses, but this is no longer allowed. Instead, the full 64MB is always allocated for each bank, and it cannot be changed.

Bank-A now always starts at 0x68000000 and Bank-B always starts at 0x6C000000 and it then follows that in the examples above:

2x 32MB dies should have:

Bank-A: 0x68000000-0x69FFFFFF
Bank-B: 0x6C000000-0x6DFFFFFF

and 2x 16MB dies should have:

Bank-A: 0x68000000-0x68FFFFFF
Bank-B: 0x6C000000-0x6CFFFFFF

...which seems to be the best-practice is you want successful production programming of your products.

Cheers!
Denis

topic Best practice for K8x QSPI Dual-Quad Address Ranges in Kinetis Microcontrollers

Best practice for K8x QSPI Dual-Quad Address Ranges