<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: MK22FN512VLL12  wafer changes and performance differences in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487459#M63551</link>
    <description>&lt;P&gt;Hi,&lt;BR /&gt;I think Bob is incorrect.&lt;BR /&gt;NXP doesn't actually want to disclose much of what the last line means, but luckily Mouser still stores an old PCN with some information:&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.mouser.com/PCN/Freescale_16780.pdf" target="_blank"&gt;https://www.mouser.com/PCN/Freescale_16780.pdf&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;Items starting with Q are assembled and tested at site in Kuala Lumpur, Malaysia&lt;BR /&gt;Items starting with XN are assembled and tested at Fujitsu-Nantong, China.&lt;BR /&gt;Wafer identifiers/lot code is AE or PK.&lt;BR /&gt;&lt;BR /&gt;The first prototype Kinetis processors where pre-fixed by P instead of M. That's why some of the first prototypes were called e.g. PK22FN512VLL12, but they're from 2013/14 and long since gone.&lt;/P&gt;</description>
    <pubDate>Mon, 11 Jul 2022 12:05:45 GMT</pubDate>
    <dc:creator>troelsoesteraa</dc:creator>
    <dc:date>2022-07-11T12:05:45Z</dc:date>
    <item>
      <title>MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486047#M63524</link>
      <description>&lt;P&gt;The new batch of materials cannot accept the boot loader. Their silk screen marking is XE (batch 2019). I took the parts we could accept the boot loader normally (silk screen marking is PK, batch 2021) to compare. X-ray is as the attachment.&lt;/P&gt;&lt;P&gt;Please help me confirm whether they have changed the wafer. If so, what has changed between them? Is the ID the same?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="[6FZ2F_MO}62}TL`]_WX(M2.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/185926i7F5DD6F2A3AE7126/image-size/medium?v=v2&amp;amp;px=400" role="button" title="[6FZ2F_MO&amp;amp;#125;62&amp;amp;#125;TL`]_WX(M2.png" alt="[6FZ2F_MO&amp;amp;#125;62&amp;amp;#125;TL`]_WX(M2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;picture 1&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="XIJ`)RAPQQVH2OSAIHKBR`G.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/185927i883913FE27C5F86A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="XIJ`)RAPQQVH2OSAIHKBR`G.png" alt="XIJ`)RAPQQVH2OSAIHKBR`G.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;picture 2 &lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="F]$3A$JVT@@8_ZB[4X(]_}Y.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/185928i4EF83E98EFAA054F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="F]$3A$JVT@@8_ZB[4X(]_&amp;amp;#125;Y.png" alt="F]$3A$JVT@@8_ZB[4X(]_&amp;amp;#125;Y.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; picture 3&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="_DNG$@)9VBY2T)949(R%(49.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/185929iC86C72B962B10317/image-size/medium?v=v2&amp;amp;px=400" role="button" title="_DNG$@)9VBY2T)949(R%(49.png" alt="_DNG$@)9VBY2T)949(R%(49.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; picture 4&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="O_`%2}C76T[%%IDWKQ~19FX.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/185930i627671F96CA1C4A6/image-size/medium?v=v2&amp;amp;px=400" role="button" title="O_`%2&amp;amp;#125;C76T[%%IDWKQ~19FX.png" alt="O_`%2&amp;amp;#125;C76T[%%IDWKQ~19FX.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;picture 5&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jul 2022 07:49:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486047#M63524</guid>
      <dc:creator>jiangzz</dc:creator>
      <dc:date>2022-07-07T07:49:47Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486064#M63526</link>
      <description>&lt;BLOCKQUOTE&gt;&lt;P&gt;The new batch of materials cannot accept the boot loader.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;I'm not sure what you mean with this. What is the problem? Are you not able to debug it?&lt;/P&gt;&lt;P&gt;As for your pictures: they are interesting, mostly they show a different PCB underneath with different traces/vias. And you see the packaging pins/leads/traces, but not the silicon itself with details.&lt;/P&gt;&lt;P&gt;As for the marking /differences: have you already checked the errata/version/marking information if it is indeed a different silicon revision or just a a different packaging series?&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jul 2022 08:12:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486064#M63526</guid>
      <dc:creator>ErichStyger</dc:creator>
      <dc:date>2022-07-07T08:12:56Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486117#M63527</link>
      <description>&lt;P&gt;Yes, we can't debug it.&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jul 2022 09:16:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486117#M63527</guid>
      <dc:creator>jiangzz</dc:creator>
      <dc:date>2022-07-07T09:16:18Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486161#M63528</link>
      <description>&lt;P&gt;Because to me you have a different PCB, I would first check that part. Other than that, I have a list of check points here: &lt;A href="https://mcuoneclipse.com/2014/11/03/debugging-failure-check-list-and-hints/" target="_blank"&gt;https://mcuoneclipse.com/2014/11/03/debugging-failure-check-list-and-hints/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;I hope this helps,&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jul 2022 10:19:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486161#M63528</guid>
      <dc:creator>ErichStyger</dc:creator>
      <dc:date>2022-07-07T10:19:00Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486494#M63538</link>
      <description>&lt;P&gt;Our problem is that we can't&amp;nbsp;accept the boot loader&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="XD3)S9`51WG6W}V18J_}WW4.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186007iA39498921A66171C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="XD3)S9`51WG6W&amp;amp;#125;V18J_&amp;amp;#125;WW4.png" alt="XD3)S9`51WG6W&amp;amp;#125;V18J_&amp;amp;#125;WW4.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="`]K$})51K73H2@DV]W2G_[Q.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186008iBD49645D371A1495/image-size/medium?v=v2&amp;amp;px=400" role="button" title="`]K$&amp;amp;#125;)51K73H2@DV]W2G_[Q.png" alt="`]K$&amp;amp;#125;)51K73H2@DV]W2G_[Q.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;The last picture in the second picture is as follows：&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="K61DK_R%{}{W2IRQJZ0NUXI.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186009i46275ADE818DD36B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="K61DK_R%{&amp;amp;#125;{W2IRQJZ0NUXI.png" alt="K61DK_R%{&amp;amp;#125;{W2IRQJZ0NUXI.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; As you can see, when accept the boot loader for the faulty chip (the silk screen is AE), his RST is faulty.&lt;/P&gt;&lt;P&gt;&amp;nbsp; The one in the upper left corner of the figure below.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="[KK]E{X)K7T@OVNV6MAYN9U.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186010iAD3AD336589B8B3E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="[KK]E{X)K7T@OVNV6MAYN9U.png" alt="[KK]E{X)K7T@OVNV6MAYN9U.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;We mainly want to know whether the firmware burned by these two different silk screen printed chips is consistent when they leave the factory, and whether the hardware design around them is consistent. Otherwise, according to our understanding, they will not be unable accept the boot loader.&lt;/P&gt;</description>
      <pubDate>Fri, 08 Jul 2022 02:08:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1486494#M63538</guid>
      <dc:creator>jiangzz</dc:creator>
      <dc:date>2022-07-08T02:08:09Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487008#M63545</link>
      <description>&lt;P&gt;Sorry maybe you have a counterfeit part&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Where did you buy your part?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 08 Jul 2022 23:00:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487008#M63545</guid>
      <dc:creator>vicentegomez</dc:creator>
      <dc:date>2022-07-08T23:00:56Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487352#M63548</link>
      <description>&lt;P&gt;This reply is missing, but he said that the Xe is an engineering sample version. He didn't look at my problem carefully. We&amp;nbsp;cannot accept the boot loader. Its silk screen is AE (xnae1935u). The silk screen of the chip that&amp;nbsp;can accept the boot loader is PK (xnpk2144u). This chip was launched in 2014. Its chip shows that it has a date code, 1935 means 35 weeks in 2019. It will be a mass production version by 2019, Where is the theory of engineering first run samples version?@bobpaddock .&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="333.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186171i2557D8ED492B3F7C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="333.png" alt="333.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;</description>
      <pubDate>Mon, 11 Jul 2022 08:45:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487352#M63548</guid>
      <dc:creator>jiangzz</dc:creator>
      <dc:date>2022-07-11T08:45:44Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487459#M63551</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;I think Bob is incorrect.&lt;BR /&gt;NXP doesn't actually want to disclose much of what the last line means, but luckily Mouser still stores an old PCN with some information:&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.mouser.com/PCN/Freescale_16780.pdf" target="_blank"&gt;https://www.mouser.com/PCN/Freescale_16780.pdf&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;Items starting with Q are assembled and tested at site in Kuala Lumpur, Malaysia&lt;BR /&gt;Items starting with XN are assembled and tested at Fujitsu-Nantong, China.&lt;BR /&gt;Wafer identifiers/lot code is AE or PK.&lt;BR /&gt;&lt;BR /&gt;The first prototype Kinetis processors where pre-fixed by P instead of M. That's why some of the first prototypes were called e.g. PK22FN512VLL12, but they're from 2013/14 and long since gone.&lt;/P&gt;</description>
      <pubDate>Mon, 11 Jul 2022 12:05:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487459#M63551</guid>
      <dc:creator>troelsoesteraa</dc:creator>
      <dc:date>2022-07-11T12:05:45Z</dc:date>
    </item>
    <item>
      <title>Re: MK22FN512VLL12  wafer changes and performance differences</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487473#M63554</link>
      <description>&lt;P&gt;Which is why I deleted my reply when I realized my error.&lt;BR /&gt;It is part numbers that start with X or have a prefix of X.&lt;BR /&gt;Not part numbers that have X in some other place.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 11 Jul 2022 12:20:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK22FN512VLL12-wafer-changes-and-performance-differences/m-p/1487473#M63554</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2022-07-11T12:20:11Z</dc:date>
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  </channel>
</rss>

