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    <title>Kinetis Microcontrollers中的主题 Interrupt handler question for kinetisKE04 i2c driver</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1468530#M63233</link>
    <description>&lt;P&gt;Thank you for all your help.&lt;/P&gt;&lt;P&gt;In the SDK_2_11_0_MKE04Z128xxx4 driver fsl_i2c.c there is the following interrupt handler.&lt;BR /&gt;Will something bad happen if I remove this last DSB instruction?　On the contrary, what does it prevent?&lt;/P&gt;&lt;P&gt;static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)&lt;BR /&gt;{&lt;BR /&gt;　　uint8_t tmpS = base-&amp;gt;S;&lt;BR /&gt;　　uint8_t tmpC1 = base-&amp;gt;C1;&lt;/P&gt;&lt;P&gt;　　/* Check if master interrupt. */&lt;BR /&gt;　　if ((0U != (tmpC1 &amp;amp; I2C_C1_MST_MASK)) || (0U != (tmpS &amp;amp; (uint8_t)kI2C_ArbitrationLostFlag)))&lt;BR /&gt;　　{&lt;BR /&gt;　　　　s_i2cMasterIsr(base, handle);&lt;BR /&gt;　　}&lt;BR /&gt;　　else&lt;BR /&gt;　　{&lt;BR /&gt;　　　　s_i2cSlaveIsr(base, handle);&lt;BR /&gt;　　}&lt;BR /&gt;　　__DSB();&lt;BR /&gt;　　}&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 03 Jun 2022 05:20:23 GMT</pubDate>
    <dc:creator>jun1</dc:creator>
    <dc:date>2022-06-03T05:20:23Z</dc:date>
    <item>
      <title>Interrupt handler question for kinetisKE04 i2c driver</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1468530#M63233</link>
      <description>&lt;P&gt;Thank you for all your help.&lt;/P&gt;&lt;P&gt;In the SDK_2_11_0_MKE04Z128xxx4 driver fsl_i2c.c there is the following interrupt handler.&lt;BR /&gt;Will something bad happen if I remove this last DSB instruction?　On the contrary, what does it prevent?&lt;/P&gt;&lt;P&gt;static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)&lt;BR /&gt;{&lt;BR /&gt;　　uint8_t tmpS = base-&amp;gt;S;&lt;BR /&gt;　　uint8_t tmpC1 = base-&amp;gt;C1;&lt;/P&gt;&lt;P&gt;　　/* Check if master interrupt. */&lt;BR /&gt;　　if ((0U != (tmpC1 &amp;amp; I2C_C1_MST_MASK)) || (0U != (tmpS &amp;amp; (uint8_t)kI2C_ArbitrationLostFlag)))&lt;BR /&gt;　　{&lt;BR /&gt;　　　　s_i2cMasterIsr(base, handle);&lt;BR /&gt;　　}&lt;BR /&gt;　　else&lt;BR /&gt;　　{&lt;BR /&gt;　　　　s_i2cSlaveIsr(base, handle);&lt;BR /&gt;　　}&lt;BR /&gt;　　__DSB();&lt;BR /&gt;　　}&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 03 Jun 2022 05:20:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1468530#M63233</guid>
      <dc:creator>jun1</dc:creator>
      <dc:date>2022-06-03T05:20:23Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt handler question for kinetisKE04 i2c driver</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1468700#M63238</link>
      <description>&lt;P&gt;Far safer to leave it.&amp;nbsp; It assures that everything is completed before the interrupt exits.&lt;BR /&gt;Taking it out leaves the system open to 'once in a blue moon', hair pulling, kid of race condition crashes.&lt;/P&gt;&lt;P&gt;For M4 based processors is is required due to errata:&lt;BR /&gt;&lt;BR /&gt;* // Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store&lt;BR /&gt;* // immediate overlapping exception return operation might vector&lt;BR /&gt;* // to incorrect interrupt&lt;BR /&gt;&lt;BR /&gt;In theory is is not required on the M0(+) cores.&lt;BR /&gt;Rarely does theory work in the Real World...&lt;BR /&gt;&lt;BR /&gt;/*&lt;BR /&gt;* Data Synchronization Barrier (DSB): Ensures that all explicit data&lt;BR /&gt;* memory transfer before the DSB are complete before any instruction&lt;BR /&gt;* after the DSB is executed.&lt;BR /&gt;*&lt;BR /&gt;* Ensure effects of an access to SCS take place before the next&lt;BR /&gt;* operation&lt;BR /&gt;*&lt;BR /&gt;* Ensure memory is updated before the next operation, for&lt;BR /&gt;* example, SVC, WFI, WFE.&lt;BR /&gt;*&lt;BR /&gt;* Vector table changes:&lt;BR /&gt;* If the program changes an entry in the vector table,&lt;BR /&gt;* and then enables the corresponding exception, a DSB&lt;BR /&gt;* instruction should be used between these two&lt;BR /&gt;* operations. This ensures that if the exception is&lt;BR /&gt;* taken after being enabled the processor uses the new&lt;BR /&gt;* exception vector. If the updated vector table is&lt;BR /&gt;* required immediately, for example if an SVC&lt;BR /&gt;* immediately follows an update to the SVC table entry&lt;BR /&gt;* via a store, then a DSB is also required.&lt;BR /&gt;*&lt;BR /&gt;* Memory Map modifications:&lt;BR /&gt;* If the system contains a memory map switching&lt;BR /&gt;* mechanism then use a DSB instruction after switching&lt;BR /&gt;* the memory map in the program. This ensures subsequent&lt;BR /&gt;* instruction execution uses the updated memory map, if&lt;BR /&gt;* the memory system makes the updated memory map visible&lt;BR /&gt;* to all subsequent memory accesses.&lt;BR /&gt;*&lt;BR /&gt;* Note:&lt;BR /&gt;* An ISB or an exception entry/return is required&lt;BR /&gt;* to ensure that the subsequent instructions are&lt;BR /&gt;* fetched using the new memory map.&lt;BR /&gt;*&lt;BR /&gt;* The memory barrier instructions, DMB and DSB, can be used to ensure&lt;BR /&gt;* that the write buffer on the processor has completed its operation&lt;BR /&gt;* before subsequent operations can be started. However, it does not&lt;BR /&gt;* check the status of the bus level write buffers. In such cases, if&lt;BR /&gt;* the system is based on AHB or AHB Lite, you might need to perform a&lt;BR /&gt;* dummy read through the bus bridge to ensure that the bus bridge has&lt;BR /&gt;* completed its operation.&lt;BR /&gt;*&lt;BR /&gt;* The Cortex-M0 processor (r0p0) and the Cortex-M0+ processor (r0p0)&lt;BR /&gt;* do not include a write buffer in their processor bus interface.&lt;BR /&gt;*&lt;BR /&gt;* Architecturally, a DSB instruction should be used after changing&lt;BR /&gt;* the VTOR if an exception is to be generated immediately and should&lt;BR /&gt;* use the latest vector table setting.&lt;BR /&gt;*&lt;BR /&gt;* In Cortex-M3, Cortex-M4 and Cortex-M0+ processors, accesses to the&lt;BR /&gt;* SCS have the DSB behavior, so there is no need to insert the DSB&lt;BR /&gt;* instruction.&lt;BR /&gt;*&lt;BR /&gt;* A DSB is required before generating self-reset to ensure all&lt;BR /&gt;* outstanding transfers are completed. The use of the CPSID I&lt;BR /&gt;* instruction is optional.&lt;BR /&gt;*/&lt;/P&gt;&lt;P&gt;// The code I use:&lt;BR /&gt;//The 'memory' clobber barrier prevents "code motion".&lt;BR /&gt;&lt;BR /&gt;#define ATTR_NO_INSTRUMENT_FUNCTION __attribute__( ( no_instrument_function ) )&lt;/P&gt;&lt;P&gt;static inline ATTR_NO_INSTRUMENT_FUNCTION void sync_barrier_data( void )&lt;BR /&gt;{&lt;BR /&gt;__asm__ __volatile__ ("dsb");&lt;BR /&gt;__asm__ __volatile__ ("" ::: "memory");&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 03 Jun 2022 11:55:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1468700#M63238</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2022-06-03T11:55:20Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt handler question for kinetisKE04 i2c driver</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1469016#M63244</link>
      <description>&lt;P&gt;Thank you for your advice.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;OK. Leave it as it is.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Also, I totally agree with the following words.&lt;/P&gt;&lt;P&gt;"Theory rarely works in the real world ..."&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;A good day&lt;/P&gt;</description>
      <pubDate>Mon, 06 Jun 2022 00:05:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interrupt-handler-question-for-kinetisKE04-i2c-driver/m-p/1469016#M63244</guid>
      <dc:creator>jun1</dc:creator>
      <dc:date>2022-06-06T00:05:50Z</dc:date>
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