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    <title>Kinetis MicrocontrollersのトピックRe: Interfacing MK64FN1M0VLQ12 with MRAM MR2A16ACMA35</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1467513#M63214</link>
    <description>&lt;P&gt;Hi, Let me check with new board design how it goes. Thank you.&lt;/P&gt;</description>
    <pubDate>Wed, 01 Jun 2022 14:02:14 GMT</pubDate>
    <dc:creator>fshah30</dc:creator>
    <dc:date>2022-06-01T14:02:14Z</dc:date>
    <item>
      <title>Interfacing MK64FN1M0VLQ12 with MRAM MR2A16ACMA35</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1452742#M63036</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am interfacing my prototype design between MK64FN1M0VLQ12 and MR2A16ACMA35. Please confirm my connections let me know if I did wrong.&lt;/P&gt;&lt;P&gt;16bit non multiplexed mode:&lt;/P&gt;&lt;P&gt;Data Lines:&lt;/P&gt;&lt;P&gt;FB_AD[31:24] =&amp;gt; DQL0 to DQU15.//Please confirm the orientation is correct?&lt;/P&gt;&lt;P&gt;DQL0 connects with DQU15&lt;/P&gt;&lt;P&gt;DQL1 connects with DQU14&lt;/P&gt;&lt;P&gt;DQL2 connects with DQU13&lt;/P&gt;&lt;P&gt;DQL3 connects with DQU12&lt;/P&gt;&lt;P&gt;DQL4 connects with DQU11&lt;/P&gt;&lt;P&gt;DQL5 connects with DQU10&lt;/P&gt;&lt;P&gt;DQL6 connects with DQU9&lt;/P&gt;&lt;P&gt;DQL7 connects with DQU8&lt;/P&gt;&lt;P&gt;Address Lines:&lt;/P&gt;&lt;P&gt;FB_AD[0:17] =&amp;gt; A[0:17] //Please confirm the orientation is correct?&lt;/P&gt;&lt;P&gt;Control Signals:&lt;/P&gt;&lt;P&gt;FB_RW_b =&amp;gt; ~W&lt;/P&gt;&lt;P&gt;FB_OE_b =&amp;gt; ~G&lt;/P&gt;&lt;P&gt;FB_CS0_b =&amp;gt; ~E&lt;/P&gt;&lt;P&gt;FB_BE7_0_BLS31_24 =&amp;gt; ~LB //Please confirm the connection&lt;/P&gt;&lt;P&gt;FB_BE15_8_BLS23_16 =&amp;gt; ~UB //Please confirm the connection&lt;/P&gt;&lt;P&gt;I hope got your reply ASAP. Thanks&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 04 May 2022 13:55:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1452742#M63036</guid>
      <dc:creator>fshah30</dc:creator>
      <dc:date>2022-05-04T13:55:45Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing MK64FN1M0VLQ12 with MRAM MR2A16ACMA35</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1464931#M63172</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/191779"&gt;@fshah30&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;The address line orientation and control signals seem fine. I just find the connection of DQL[7:0] to DQU [8:15] confusing. What are you trying to achieve with these connections?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR,&lt;/P&gt;
&lt;P&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Thu, 26 May 2022 16:25:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1464931#M63172</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2022-05-26T16:25:07Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing MK64FN1M0VLQ12 with MRAM MR2A16ACMA35</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1465051#M63175</link>
      <description>&lt;P&gt;Hi Edwin,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I want to interface parallel MRAM with MK64FN1M0VLQ12. I got this interface schematic please confirm if I go with same connections. Please advise if I can use the attached MRAM interface&amp;nbsp;@Page#4&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;</description>
      <pubDate>Thu, 26 May 2022 21:00:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1465051#M63175</guid>
      <dc:creator>fshah30</dc:creator>
      <dc:date>2022-05-26T21:00:04Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing MK64FN1M0VLQ12 with MRAM MR2A16ACMA35</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1465704#M63183</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/191779"&gt;@fshah30&lt;/a&gt;.,&lt;/P&gt;
&lt;P&gt;Alright, the connections for the MRAM seem good. You can use this as base for the connections with your MK64.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR,&lt;/P&gt;
&lt;P&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Fri, 27 May 2022 16:10:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1465704#M63183</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2022-05-27T16:10:23Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing MK64FN1M0VLQ12 with MRAM MR2A16ACMA35</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1467513#M63214</link>
      <description>&lt;P&gt;Hi, Let me check with new board design how it goes. Thank you.&lt;/P&gt;</description>
      <pubDate>Wed, 01 Jun 2022 14:02:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Interfacing-MK64FN1M0VLQ12-with-MRAM-MR2A16ACMA35/m-p/1467513#M63214</guid>
      <dc:creator>fshah30</dc:creator>
      <dc:date>2022-06-01T14:02:14Z</dc:date>
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