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    <title>Kinetis MicrocontrollersのトピックRe: What is the clock source for TSTMR in the K32L2A?</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1431519#M62704</link>
    <description>&lt;P&gt;Hi bobpaddock,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Sorry for the inconvenience we bring you!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;It is confirmed that there is a 1MHz output from the SIRC that runs whenever the SIRC is enabled and is used to clock the TSTMR.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;BR /&gt;Robin&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 22 Mar 2022 01:06:38 GMT</pubDate>
    <dc:creator>Robin_Shen</dc:creator>
    <dc:date>2022-03-22T01:06:38Z</dc:date>
    <item>
      <title>What is the clock source for TSTMR in the K32L2A?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1418517#M62504</link>
      <description>&lt;P&gt;The data sheet for the K32L never gives a clear source for where the TSTMR clock comes from.&lt;BR /&gt;What follows are the various reference related to TSTMR scattered through the Reference Manual.&lt;BR /&gt;&lt;BR /&gt;Anyone have answer?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;"&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;The TSTMR runs off the 1 MHz clock and resets on every system reset."&lt;/SPAN&gt;&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="112"&gt;&lt;SPAN class=""&gt;TSTMR&lt;/SPAN&gt;&lt;/TD&gt;&lt;TD width="111"&gt;&lt;SPAN class=""&gt;SIRCLK @ 1 MHz&lt;/SPAN&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="223"&gt;&lt;SPAN class=""&gt;Chip Reset DIVSLOW_CLK&lt;/SPAN&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;BR /&gt;"&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;In addition to the run mode when the device resets, the DIVCORE_CLK divide ratio is&lt;BR /&gt;determined by the NVM (IFR) options. The IFR bits set the DIVCORE field in the&lt;BR /&gt;SCG’s Run Clock Control Register (SCG_RCCR). Similarly the DIVSLOW_CLK divide&lt;BR /&gt;ratio is also determined by the NVM (IFR) options.&lt;BR /&gt;&lt;BR /&gt;Out of reset, the SIRC module is enabled and used as the main clock source out of reset.&lt;BR /&gt;This provides an 8MHz source clock&lt;/SPAN&gt;&amp;nbsp;"&lt;BR /&gt;&lt;BR /&gt;By default DIVCORE_CLK is divide by 1, DIVSLOW_CLK is divide by 2, giving 4 MHz at reset.&amp;nbsp; Is there a divide by 4 in the TSTMR to get 1 MHz?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;fsl_tstmr.h implies that the clock can be 1 MHz or 8 MHz:&lt;BR /&gt;&lt;SPAN&gt;&lt;BR /&gt;/*!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;* @brief Delays for a specified number of microseconds.&lt;BR /&gt;*&lt;BR /&gt;* This function repeatedly reads the timestamp register and waits for the user-specified&lt;BR /&gt;* delay value.&lt;BR /&gt;*&lt;BR /&gt;* @param base TSTMR peripheral base address.&lt;BR /&gt;* @param delayInUs Delay value in microseconds.&lt;BR /&gt;*/&lt;BR /&gt;static inline void TSTMR_DelayUs(TSTMR_Type *base, uint32_t delayInUs)&lt;BR /&gt;{&lt;BR /&gt;uint64_t startTime = TSTMR_ReadTimeStamp(base);&lt;/P&gt;&lt;P&gt;#if defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ) &amp;amp;&amp;amp; FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ&lt;/P&gt;&lt;P&gt;while (TSTMR_ReadTimeStamp(base) - startTime &amp;lt; delayInUs)&lt;/P&gt;&lt;P&gt;#elif defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ) &amp;amp;&amp;amp; FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ&lt;/P&gt;&lt;P&gt;while (TSTMR_ReadTimeStamp(base) - startTime &amp;lt; 8 * delayInUs)&lt;/P&gt;&lt;P&gt;#else&lt;/P&gt;&lt;P&gt;assert(0);&lt;/P&gt;&lt;P&gt;#endif&lt;BR /&gt;{&lt;BR /&gt;}&lt;BR /&gt;}&lt;/P&gt;</description>
      <pubDate>Wed, 23 Feb 2022 18:08:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1418517#M62504</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2022-02-23T18:08:56Z</dc:date>
    </item>
    <item>
      <title>Re: What is the clock source for TSTMR in the K32L2A?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1431519#M62704</link>
      <description>&lt;P&gt;Hi bobpaddock,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Sorry for the inconvenience we bring you!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;It is confirmed that there is a 1MHz output from the SIRC that runs whenever the SIRC is enabled and is used to clock the TSTMR.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;BR /&gt;Robin&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 22 Mar 2022 01:06:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1431519#M62704</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2022-03-22T01:06:38Z</dc:date>
    </item>
    <item>
      <title>Re: What is the clock source for TSTMR in the K32L2A?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1431986#M62711</link>
      <description>&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 22 Mar 2022 12:38:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-is-the-clock-source-for-TSTMR-in-the-K32L2A/m-p/1431986#M62711</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2022-03-22T12:38:14Z</dc:date>
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