K70 UART2 with Hardware fifo not working.

aseem — Sat, 21 Sep 2013 13:56:30 GMT

Hi all,

I'm working on K70 microcontroller.

I've successfully implemented uart driver without hardware fifo. ( 8-E-1 38400 baud rate)

Receive in Interrupt mode and Transmit in Polling mode.

Now I want to use hardware fifo. However after enabling hardware fifo its not working, not going in ISR routine.

below is my code. Please correct me where I'm doing wrong

SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;

SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;

PORTE->PCR[17] = (3UL << 8);

PORTE->PCR[16] = (3UL << 8);

UART2->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK);

UART2->C1 = 0; /* We need all default settings, so entire register is cleared */

br = ((60000000)/(38400 * 16));

temp = UART2->BDH & ~(UART_BDH_SBR(0x1F));
UART2->BDH = temp | UART_BDH_SBR(((br & 0x1F00) >> 8));
UART2->BDL = (unsigned char)(br & UART_BDL_SBR_MASK);

brfa = (((60000000*32)/(38400 * 16)) - (br * 32));
temp =UART2->C4 & ~(UART_C4_BRFA(0x1F));
UART2->C4 = temp | UART_C4_BRFA(brfa);
UART2->C1 |= (UART_C1_M_MASK | UART_C1_PE_MASK); /* Even parity */

UART2->S2 = 0x00;
UART2->C3 = 0x00;

/********************* added below code for hardware fifo ****************/

UART2->PFIFO |= 0x08;
UART2->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
UART2->CFIFO &= ~UART_CFIFO_RXFLUSH_MASK;
/*********************************************************************************/

// UART2->RWFIFO = UART_RWFIFO_RXWATER(1); /* without fifo */

UART2->RWFIFO = UART_RWFIFO_RXWATER(2); /* with fifo */
UART2->TWFIFO = UART_TWFIFO_TXWATER(0);

NVIC_EnableIRQ(UART2_RX_TX_IRQn);

UART2->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK| UART_C2_RIE_MASK) ;

Thanks in advance..

Re: K70 UART2 with Hardware fifo not working.

jeremyzhou — Sun, 22 Sep 2013 06:52:25 GMT

Hi Aseem,

According the standard feature of UART which is describled in Chart 3 Chip Cofigruation of reference manual. The UART2 contain a 1-entry transmit and receive FIFOs(Fig 1) and the proper value be set in the RXWATER muste be less than the size of the Receive buffer/FIFO size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and greater than 0(Fig 2). So I think you should check the code

UART2->RWFIFO = UART_RWFIFO_RXWATER(2); /* with fifo */ which set the size of FIFO is 2.

Fig 1

Fig 2

Regards,

Ping

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K70 UART2 with Hardware fifo not working.

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