MK10 PLL clock configuration

davithakobyan — Wed, 15 Sep 2021 09:21:43 GMT

Hi,

I try to run a sample project for MK10DN512VLL10 by configuring the clock to use the external OSC and run at 100 MHz of PLL. However, the execution hangs in a while loop for waiting the clock source to be set to external clock reference. The relevant parts are as follows:

Configuration part

const mcg_config_t mcgConfig_BOARD_BootClockRUN = { .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */ .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ .vdiv = 0x1aU, /* VCO divider: multiplied by 50 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockRUN = { .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ .er32ksrc=SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ .clkdiv1 = 0x1130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /4 */ }; const osc_config_t oscConfig_BOARD_BootClockRUN = { .freq = 8000000U, /* Oscillator frequency: 8000000Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeExt, /* Use external clock */ .oscerConfig = { .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ } };

Setting up the clock

void BOARD_BootClockRUN(void) { /* Set the system clock dividers in SIM to safe value. */ CLOCK_SetSimSafeDivs(); /* Initializes OSC0 according to board configuration. */ CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN); CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); /* Configure FLL external reference divider (FRDIV). */ CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); /* Set MCG to PEE mode. */ CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockRUN.pll0Config); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; }

The problem occurs in the above CLOCK_BootToPeeMode function. Particularly, it hangs in the following check:

while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) { }

Does anyone know the reason why it is not possible to set the external ref. clock?

Does anyone have a working clock initialization procedure which one could use?

Thanks a lot in advance.

Re: MK10 PLL clock configuration

Robin_Shen — Thu, 16 Sep 2021 08:48:11 GMT

Hi davithakobyan,

Are you using an external crystal or external reference clock source?

Here is the difference:

In addition, you can also check if there is a matching errata.

Please check the mask of MCU, make sure the part number is MK10DN512VLL10 not MK10DN512ZVLL10

The codes shown below belong to CLOCK_BootToBlpeMode and CLOCK_SetPbeMode. Did you call these function?

    while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
    {
    }

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

topic Re: MK10 PLL clock configuration in Kinetis Microcontrollers

MK10 PLL clock configuration

Re: MK10 PLL clock configuration