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    <title>topic IMXRT1024 LPUART, eDMA and OCRAM Relationship in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IMXRT1024-LPUART-eDMA-and-OCRAM-Relationship/m-p/1330995#M61359</link>
    <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am stuck with a&amp;nbsp;relationship triangle&amp;nbsp;(LPUART, eDMA, ADMA and OCRAM). I just want to use eDMA with LPUART and trying to monitor my transmit and receive datas on the RAM. Here is my nested path from Reference Manual.&lt;/P&gt;&lt;P&gt;In &lt;STRONG&gt;6.2 Overview&lt;/STRONG&gt; it says:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;EM&gt;Local memory containing transfer control descriptors for each of the 32 channels&lt;/EM&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;In &lt;STRONG&gt;6.2.3 Features&amp;nbsp;&lt;/STRONG&gt;it says:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;TCD supports two-deep, nested transfer operations&lt;BR /&gt;• 32-byte TCD stored in local memory for each channel&lt;BR /&gt;• An inner data transfer loop defined by a minor byte transfer count&lt;BR /&gt;• An outer data transfer loop defined by a major iteration count&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;In&amp;nbsp;&lt;STRONG&gt;Figure 9-2. Internal ROM and RAM memory map&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;NOTE &lt;/STRONG&gt;it says&lt;STRONG&gt;:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Lukas_Frank_1-1630062051463.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154327iD025D64B7E3C7A51/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Lukas_Frank_1-1630062051463.png" alt="Lukas_Frank_1-1630062051463.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In&amp;nbsp;&lt;STRONG&gt;Figure 26-11. Concept and access method of the ADMA2 descriptor table&amp;nbsp;&lt;/STRONG&gt;it says:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Lukas_Frank_2-1630062217724.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154328i26D88DC14246CE17/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Lukas_Frank_2-1630062217724.png" alt="Lukas_Frank_2-1630062217724.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;So I have following question:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q1:&lt;/STRONG&gt; What is the difference between eDMA and ADMA?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q2:&lt;/STRONG&gt; Where will create my eDMA's TCD in the memory(RAM)? So, Which address interval?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q3:&lt;/STRONG&gt; How can I monitor my eDMA LPUART receive and transmit datas on RAM in MCUExpresso IDE in debug time?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and Regards.&lt;/P&gt;</description>
    <pubDate>Fri, 27 Aug 2021 11:07:41 GMT</pubDate>
    <dc:creator>Lukas_Frank</dc:creator>
    <dc:date>2021-08-27T11:07:41Z</dc:date>
    <item>
      <title>IMXRT1024 LPUART, eDMA and OCRAM Relationship</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IMXRT1024-LPUART-eDMA-and-OCRAM-Relationship/m-p/1330995#M61359</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am stuck with a&amp;nbsp;relationship triangle&amp;nbsp;(LPUART, eDMA, ADMA and OCRAM). I just want to use eDMA with LPUART and trying to monitor my transmit and receive datas on the RAM. Here is my nested path from Reference Manual.&lt;/P&gt;&lt;P&gt;In &lt;STRONG&gt;6.2 Overview&lt;/STRONG&gt; it says:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;EM&gt;Local memory containing transfer control descriptors for each of the 32 channels&lt;/EM&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;In &lt;STRONG&gt;6.2.3 Features&amp;nbsp;&lt;/STRONG&gt;it says:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;TCD supports two-deep, nested transfer operations&lt;BR /&gt;• 32-byte TCD stored in local memory for each channel&lt;BR /&gt;• An inner data transfer loop defined by a minor byte transfer count&lt;BR /&gt;• An outer data transfer loop defined by a major iteration count&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;In&amp;nbsp;&lt;STRONG&gt;Figure 9-2. Internal ROM and RAM memory map&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;NOTE &lt;/STRONG&gt;it says&lt;STRONG&gt;:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Lukas_Frank_1-1630062051463.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154327iD025D64B7E3C7A51/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Lukas_Frank_1-1630062051463.png" alt="Lukas_Frank_1-1630062051463.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In&amp;nbsp;&lt;STRONG&gt;Figure 26-11. Concept and access method of the ADMA2 descriptor table&amp;nbsp;&lt;/STRONG&gt;it says:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Lukas_Frank_2-1630062217724.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154328i26D88DC14246CE17/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Lukas_Frank_2-1630062217724.png" alt="Lukas_Frank_2-1630062217724.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;So I have following question:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q1:&lt;/STRONG&gt; What is the difference between eDMA and ADMA?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q2:&lt;/STRONG&gt; Where will create my eDMA's TCD in the memory(RAM)? So, Which address interval?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q3:&lt;/STRONG&gt; How can I monitor my eDMA LPUART receive and transmit datas on RAM in MCUExpresso IDE in debug time?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and Regards.&lt;/P&gt;</description>
      <pubDate>Fri, 27 Aug 2021 11:07:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IMXRT1024-LPUART-eDMA-and-OCRAM-Relationship/m-p/1330995#M61359</guid>
      <dc:creator>Lukas_Frank</dc:creator>
      <dc:date>2021-08-27T11:07:41Z</dc:date>
    </item>
    <item>
      <title>Re: IMXRT1024 LPUART, eDMA and OCRAM Relationship</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IMXRT1024-LPUART-eDMA-and-OCRAM-Relationship/m-p/1337985#M61455</link>
      <description>&lt;P&gt;Hello Lukas_Frank,&lt;/P&gt;
&lt;P&gt;I see that some of your questions have been answered on other threads. I’m adding a link for reference in case it helps other users.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-RT/IMXRT1024-LPUART-eDMA-RAM-Location-and-Limitation/m-p/1329191" target="_blank"&gt;https://community.nxp.com/t5/i-MX-RT/IMXRT1024-LPUART-eDMA-RAM-Location-and-Limitation/m-p/1329191&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;I think the matter that was not covered would be the differences between eDMA and ADMA. The Advanced DMA (ADMA) is a transfer algorithm used by the SD Host Controller so it’s a different DMA algorithm. There are more details on how it’s handled on the i.MXRT1024 Reference Manual on the uSDHC chapter as it’s main application is being compliant with the uSDHC standard.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Gustavo&lt;/P&gt;</description>
      <pubDate>Fri, 10 Sep 2021 01:51:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IMXRT1024-LPUART-eDMA-and-OCRAM-Relationship/m-p/1337985#M61455</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2021-09-10T01:51:02Z</dc:date>
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