topic Re: Regarding errata e10180 in Kinetis Microcontrollers

Regarding errata e10180

aporvasrivastava — Wed, 11 Aug 2021 16:05:49 GMT

Hi Team,

While analyzing errata e10180, description says that Clock switch may hang if SCG_RCCR is written to the switch system clock source with a different divide ratio while an external reset is asserted.

I have doubt that controller is getting up and external reset is de-asserted then how software can updated SCG_RCCR register when external reset is asserted.

Please let me know if this understanding is correct ?

Re: Regarding errata e10180

jingpan — Thu, 12 Aug 2021 09:40:15 GMT

Hi @aporvasrivastava ,

The risk of clock hanging during switch is due to the internal timing, the scenario is: The silicon is booting up on FIRC and then the RCCR register is written by user's code to switch the system clock to SIRC. But as soon as the RCCR register is written as SIRC clock, the external reset is asserted, due to which the SCS bus moved to RESET value which is FIRC, but the SCS_NEXT stayed at 'h2 (SIRC) as ipg_clk is cut on reset. due to reset while boot up again the clock process is hanging as the SCS and SCS_NEXT is not matching due to scs_next not resetting.

Regards,

Jing

Re: Regarding errata e10180

bobpaddock — Thu, 12 Aug 2021 12:19:10 GMT

Where do I find this Errata?

Did not find it via using search on NXP site.

Re: Regarding errata e10180

jingpan — Fri, 13 Aug 2021 02:13:13 GMT

Hi,

Please get from here

https://www.nxp.com/docs/en/errata/Kinetis_E_0N79P.pdf

Regards

Re: Regarding errata e10180

bobpaddock — Fri, 13 Aug 2021 13:40:26 GMT

Thank you.