topic Re: LPSPI in MKE18F512VLL16 in Kinetis Microcontrollers

LPSPI in MKE18F512VLL16

CEPL_Dev — Thu, 18 Feb 2021 09:28:23 GMT

Hello friends,

I'm trying to use the LPSPI module of Kinetis MKE18F512VLL16 for making a single byte transfer function. I tried to drive the peripheral with both the CMSIS LPSPI driver as well as the NXP Peripheral SDK Library. Tried example codes for both of the libraries with transfer size set to 1. Every time when I run the code, the data transfer function got stuck in the below mentioned while loop and it's not going forward.

I tried debugging step by step, but couldn't find a solution. So I went forward and wrote a bare-metal driver for LPSPI from scratch and that didn't worked either. The bare- metal driver is as follows.

void InitSPI(void){

/* Set pin mux alternative to LPSPI */

PORTB->PCR[14] |= PORT_PCR_MUX(3);

PORTB->PCR[15] |= PORT_PCR_MUX(3);

PORTB->PCR[16] |= PORT_PCR_MUX(3);

PORTB->PCR[17] |= PORT_PCR_MUX(3);

PCC->CLKCFG[PCC_LPSPI1_INDEX] |= PCC_CLKCFG_CGC(0b1);

/* Enable Clock for LPSPI Module */

PCC->CLKCFG[PCC_LPSPI1_INDEX] |= PCC_CLKCFG_PCS(3);

/* FIRC selected as clock source */

LPSPI1->CR |= LPSPI_CR_RTF_MASK; /* Reset Transmit FIFO */

LPSPI1->CR |= LPSPI_CR_RRF_MASK; /* Reset Receive FIFO */

LPSPI1->CR |= LPSPI_CR_DBGEN_MASK; /* Module is enabled in debug mode */

LPSPI1->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; /* Output data is tristated when CS is negated */

LPSPI1->CFGR1 |= LPSPI_CFGR1_MASTER_MASK; /* Master Mode configured */

LPSPI1->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); /* No Stall Disabled */

LPSPI1->CCR |= LPSPI_CCR_SCKPCS(1); /* Delay from the last SCK edge to the PCS negation */

LPSPI1->CCR |= LPSPI_CCR_PCSSCK(1); /* Delay from the PCS assertion to the first SCK edge */

LPSPI1->CCR |= LPSPI_CCR_DBT(2); /* Delay from the PCS negation to the next PCS assertion */

LPSPI1->CCR |= LPSPI_CCR_SCKDIV(2); /* SCK Divider */

LPSPI1->FCR |= LPSPI_FCR_RXWATER(1); /* Receive FIFO Watermark */

LPSPI1->FCR |= LPSPI_FCR_TXWATER(1); /* Transmit FIFO Watermark */

LPSPI1->TCR &= ~(LPSPI_TCR_TXMSK_MASK); /* Trasmit Masked */

LPSPI1->TCR |= LPSPI_TCR_RXMSK(1); /* Receive Masked */

LPSPI1->TCR |= LPSPI_TCR_PRESCALE(3); /* Prescale - 8 */

LPSPI1->TCR |= LPSPI_TCR_WIDTH(1); /* LPSPI in 2 wire mode */

LPSPI1->TCR |= LPSPI_TCR_PCS(3); /* Trasfer using PCS 3 */

LPSPI1->TCR |= LPSPI_TCR_FRAMESZ(8); /* Frame Size 8 bits */

LPSPI1->TCR |= LPSPI_TCR_TXMSK_MASK; /* Trasmit Unmasked */

LPSPI1->CR |= LPSPI_CR_MEN_MASK; /* Module is enabled */

/* Baud Rate = (SrcClk/PRESCALE)/(SCKDIV+2) = (12MHz/8)/(4) = 375 KHz */

}

void SPISendData(uint8_t TxData){

LPSPI1->TCR |= LPSPI_TCR_RXMSK(1); /* Receive Masked */

LPSPI1->TCR |= LPSPI_TCR_TXMSK_MASK; /* Trasmit Unmasked */

LPSPI1->TDR = TxData;

}

uint32_t SPI_ReadData(void){

LPSPI1->TCR &= ~LPSPI_TCR_RXMSK(1); /* Receive Unmasked */

LPSPI1->TCR &= ~(LPSPI_TCR_TXMSK_MASK); /* Trasmit Masked */

return (LPSPI1->RDR);

}

1. What could be the reason behind the NXP LPSPI SDK peripheral library example code getting stuck in the above mentioned while loop for checking FIFO.

2. What could be wrong in the bare metal code which was written for a single byte transfer.

Thank you,

Prasanth K S

Re: LPSPI in MKE18F512VLL16

bobpaddock — Thu, 18 Feb 2021 13:36:20 GMT

Using '|=' almost everyplace is likely clearing some needed status bit.
NXP has a bad habit of using |= when it is not needed.
At best this wastes code space at worse it makes broken code.

Re: LPSPI in MKE18F512VLL16

kerryzhou — Fri, 19 Feb 2021 06:12:08 GMT

Hi CEPL_Dev,

Do you mean, just when you modify single byte transfer function in the SDK, you meet the stuck issues?

Do you test the SDK code:

SDK_2.8.0_TWR-KE18F\boards\twrke18f\driver_examples\lpspi\polling_b2b_transfer\master

directly? Any issues or not?

Today, I test our SDK code, just the above master project, I modify the renasfer size to 1 byte, it works Ok:

You can find, I run over LPSPI_MasterTransferBlocking :

while (LPSPI_GetTxFifoCount(base) == fifoSize)
{
}

BTW, I also test the interrupt code:

SDK_2.8.0_TWR-KE18F\boards\twrke18f\driver_examples\lpspi\interrupt_b2b\master

Even I modify the byte to 1, it also works OK.

So, you can try the SDK code directly.

If you still have questions about it, please kindly let me know.

Best Regards,

kerry

Re: LPSPI in MKE18F512VLL16

ArmandoPinedaM — Mon, 30 May 2022 13:59:06 GMT

Hi!
I was testing the MKE18F512XXX16 LPSPI example but in a custom MKE16F512XXX16 board (MKE16 SDK didn't came with an example so I copied the example for a TWR board).

I was having the same issue that you, my LPSPI_MasterTransferNonBlocking function got stucked everytime in that exact place

while (LPSPI_GetTxFifoCount(base) != 0U)

I was debugging and detected that base->TCR had a value of 1 and wasnt changing.

At the end I discovered that it was a problem of my clock configuration because the SPI wasn't running.
If the SPI clock isnt configured correctly it wont run.

At the beginning of my example code I had this:

srcClock_Hz = LPSPI_MASTER_CLK_FREQ;
LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz);

And I found that srcClock_Hz got loaded with 0 instead of the real value.

All I did was checking my clock and preescaler config so it is running at correct speed.

This is my configuration:

/*******************************************************************************
* Definitions
******************************************************************************/
#define EXAMPLE_LPSPI_MASTER_BASEADDR LPSPI0
#define EXAMPLE_LPSPI_MASTER_CLOCK_NAME kCLOCK_Lpspi0
#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetIpFreq(EXAMPLE_LPSPI_MASTER_CLOCK_NAME))
#define EXAMPLE_LPSPI_MASTER_CLOCK_SOURCE (kCLOCK_IpSrcSircAsync)
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT kLPSPI_Pcs2
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER kLPSPI_MasterPcs2
#define EXAMPLE_LPSPI_DEALY_COUNT 0xfffff
#define TRANSFER_SIZE 64U /*! Transfer dataSize */
#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */

And my clock config:

SIRC DIV1 clock: 8MHz
SIRC DIV2 clock: 4MHz

Hope this helps.

Re: LPSPI in MKE18F512VLL16

kerryzhou — Tue, 31 May 2022 01:30:06 GMT

Hi @ArmandoPinedaM ,

Any new issues, please create the your own question post, then our kinetis engineer will help you.

Best Regards,

kerry