<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Kinetis Microcontrollers中的主题 Re: MKL28Z SRAM question</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1229787#M59596</link>
    <description>&lt;P&gt;Thanks for your confirmation.&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 11 Feb 2021 09:56:06 GMT</pubDate>
    <dc:creator>benwang</dc:creator>
    <dc:date>2021-02-11T09:56:06Z</dc:date>
    <item>
      <title>MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227694#M59550</link>
      <description>&lt;P&gt;Hi, I am taking a lot at the &lt;STRONG&gt;MKL28Z&lt;/STRONG&gt; reference manual , and did not about if the internal SRAM(128k) is split into two regions as MKL27Z, which are SRAM_L and SRAM_U?&amp;nbsp; Does MKL28Z did split into two same size of SRAM_L(64KB:&amp;nbsp;0x1fff8000~1fffffff) and SRAM_U(64KB:0x20000000~0x20007ffff)&amp;nbsp;as the general feature as other Kinetis MCU?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 05:46:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227694#M59550</guid>
      <dc:creator>benwang</dc:creator>
      <dc:date>2021-02-08T05:46:43Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227712#M59551</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/168"&gt;@benwang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;To my understanding, only the Kinetis family without the L has a dual memory controller and that's why the memory is split around 0x2000'0000. But the L family does not have such a split:&lt;/P&gt;&lt;P&gt;KL28Z:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ErichS_0-1612764556606.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/136723i2FE0B0E4EEFCA2FE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ErichS_0-1612764556606.png" alt="ErichS_0-1612764556606.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;KL27Z:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ErichS_1-1612764604181.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/136724i519E43BC4FE5C132/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ErichS_1-1612764604181.png" alt="ErichS_1-1612764604181.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope this helps,&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;&lt;P&gt;PS: as for the implications of the divided memory on the K devices, there is a discussion on this topic on &lt;A href="https://mcuoneclipse.com/2017/09/18/using-multiple-memory-regions-with-the-freertos-heap/" target="_self"&gt;Using Multiple Memory Regions with the FreeRTOS Heap&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 06:14:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227712#M59551</guid>
      <dc:creator>ErichStyger</dc:creator>
      <dc:date>2021-02-08T06:14:32Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227959#M59555</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/17173"&gt;@ErichStyger&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Thanks for you quick reply. But according to the MKL27Z reference manual, it dos split the SRAM into SRAM_L and SRAM_U, please refer to the page 60.&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com.cn/docs/en/reference-manual/KL27P64M48SF6RM.pdf" target="_blank"&gt;https://www.nxp.com.cn/docs/en/reference-manual/KL27P64M48SF6RM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;However, I did not find the similar description on MKL28Z, that's why I am a little bit confused about this. Could you double confirm with AE or design team about that? Thanks!&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com.cn/docs/en/reference-manual/MKL28ZRM.pdf" target="_blank"&gt;https://www.nxp.com.cn/docs/en/reference-manual/MKL28ZRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 12:29:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227959#M59555</guid>
      <dc:creator>benwang</dc:creator>
      <dc:date>2021-02-08T12:29:05Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227965#M59557</link>
      <description>&lt;P&gt;So either the SDK or the RM is wrong, I believe the later (or at least misleading).&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 12:47:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1227965#M59557</guid>
      <dc:creator>ErichStyger</dc:creator>
      <dc:date>2021-02-08T12:47:16Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1228009#M59558</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;The SRAM layout in the KL28 is the same as in all other L parts:&lt;BR /&gt;1/4 anchored below 0x20000000&lt;BR /&gt;3/4 anchored above 0x20000000&lt;BR /&gt;&lt;BR /&gt;In the manual it is show in two places:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mjbcswitzerland_0-1612792062328.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/136761i6B026C3D2E2D10BF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mjbcswitzerland_0-1612792062328.png" alt="mjbcswitzerland_0-1612792062328.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mjbcswitzerland_1-1612792091482.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/136762iBB1DEDF278A51BAD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mjbcswitzerland_1-1612792091482.png" alt="mjbcswitzerland_1-1612792091482.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;although it is a strange that in the first table the first 1/4 of the SRAM is in the code section rather than in the SRAM section.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Mark&lt;BR /&gt;&lt;EM&gt;[uTasker project developer for Kinetis and i.MX RT]&lt;/EM&gt;&lt;BR /&gt;&lt;FONT color="#999999"&gt;Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or rapid product development requirements&lt;BR /&gt;&lt;BR /&gt;For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: &lt;A href="https://www.utasker.com/kinetis/FRDM-KL28Z.html" target="_blank"&gt;https://www.utasker.com/kinetis/FRDM-KL28Z.html&lt;/A&gt;&lt;BR /&gt;&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 13:50:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1228009#M59558</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2021-02-08T13:50:32Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1228430#M59578</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1431"&gt;@mjbcswitzerland&lt;/a&gt;&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/17173"&gt;@ErichStyger&lt;/a&gt;&amp;nbsp;Thanks for your answer. But still looks like we did not come to agreement about this. It's better we could ask for AE team or IC design team to get the accurate &lt;A href="mailto:feedback.@chen" target="_blank"&gt;feedback&amp;nbsp;&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 09 Feb 2021 03:19:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1228430#M59578</guid>
      <dc:creator>benwang</dc:creator>
      <dc:date>2021-02-09T03:19:29Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1228434#M59580</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;I have used the KL28 with this SRAM layout so am very sure that it is accurate, otherwise I am sure that the projects would already have failed to run correctly.&lt;/P&gt;&lt;P&gt;This reference has been on line for over three years: &lt;A href="https://www.utasker.com/kinetis/FRDM-KL28Z.html" target="_blank"&gt;https://www.utasker.com/kinetis/FRDM-KL28Z.html&lt;/A&gt; using the SRAM as specified with no reports of failure.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 09 Feb 2021 03:24:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1228434#M59580</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2021-02-09T03:24:45Z</dc:date>
    </item>
    <item>
      <title>Re: MKL28Z SRAM question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1229787#M59596</link>
      <description>&lt;P&gt;Thanks for your confirmation.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 11 Feb 2021 09:56:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL28Z-SRAM-question/m-p/1229787#M59596</guid>
      <dc:creator>benwang</dc:creator>
      <dc:date>2021-02-11T09:56:06Z</dc:date>
    </item>
  </channel>
</rss>

