<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Kinetis MicrocontrollersのトピックRe: SPI DMA K66</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1177670#M58723</link>
    <description>&lt;P&gt;The problem I am facing is after triggering the DMA the data is loading into push register but after completion of transfer the TCF bit is setted which is not cleared automatically when i use DMA&lt;/P&gt;</description>
    <pubDate>Wed, 04 Nov 2020 04:32:36 GMT</pubDate>
    <dc:creator>mdrasool_yadwad</dc:creator>
    <dc:date>2020-11-04T04:32:36Z</dc:date>
    <item>
      <title>SPI DMA K66</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1175697#M58678</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; I having configured SPI2 for communication with external EEPROM(SPI supported) using DMA.&lt;/P&gt;&lt;P&gt;I am not able to write the data on the external EEPROM correctly.&lt;/P&gt;&lt;P&gt;I am writing data using DMA channel 0 and reading using DMA channel 1.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I don't know what's the problem and I am stuck in to it.&amp;nbsp;&lt;/P&gt;&lt;P&gt;below is my code please correct me if I am wrong&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;//SPI2 configuration&lt;/P&gt;&lt;P&gt;//--&amp;gt;Disable SPI&lt;BR /&gt;Spix-&amp;gt;MCR |=0x01;&lt;BR /&gt;Spix-&amp;gt;MCR &amp;amp;= (~SPI_MCR_MDIS_MASK);&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt;SPI in Master mode&lt;BR /&gt;Spix-&amp;gt;MCR |= SPI_MCR_MSTR_MASK;&lt;BR /&gt;&lt;BR /&gt;Spix-&amp;gt;MCR |= SPI_MCR_ROOE_MASK;&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt;Enabling continuous clock&lt;BR /&gt;// Spix-&amp;gt;MCR &amp;amp;=~SPI_MCR_CONT_SCKE_MASK;&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt; Disable Rx FIFO&lt;BR /&gt;Spix-&amp;gt;MCR|=SPI_MCR_DIS_RXF_MASK;&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt; Disable Tx FIFO&lt;BR /&gt;Spix-&amp;gt;MCR|=SPI_MCR_DIS_TXF_MASK;&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt;Clear RX and TX FIFO counters&lt;BR /&gt;Spix-&amp;gt;MCR|=SPI_MCR_CLR_RXF_MASK;&lt;BR /&gt;Spix-&amp;gt;MCR|=SPI_MCR_CLR_TXF_MASK;&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt;Peripheral Chip Select is Inactive Low&lt;BR /&gt;Spix-&amp;gt;MCR |=SPI_MCR_PCSIS(1&amp;lt;&amp;lt;0);&lt;BR /&gt;&lt;BR /&gt;//--&amp;gt;Frame Size&lt;BR /&gt;Spix-&amp;gt;CTAR[0]= SPI_CTAR_FMSZ(0x07);&lt;BR /&gt;&lt;BR /&gt;// BAUDRATE_625KHZ:&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_PBR(0x01);&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_BR(0x05);&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_DBR(0);&lt;BR /&gt;&lt;BR /&gt;//SpiSetClockPhase&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_CPHA(0x00);&lt;BR /&gt;&lt;BR /&gt;//SpiSetClockPolarity&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_CPOL(0x00);&lt;BR /&gt;&lt;BR /&gt;//MSB First&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_LSBFE(0x00);&lt;BR /&gt;&lt;BR /&gt;//SpiSetDelayAfterTX&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_DT(0x01);&lt;BR /&gt;&lt;BR /&gt;//SetDelayAfterSCK&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_ASC(0x01);&lt;BR /&gt;&lt;BR /&gt;//SetDelayAfterPCS&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_CSSCK(0x01);&lt;BR /&gt;&lt;BR /&gt;//SpiSetDelayAfterPCSSCK&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_PCSSCK(0x00);&lt;BR /&gt;&lt;BR /&gt;//SpiSetDelayAfterPDT&lt;BR /&gt;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_PASC(0x00);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; //SpiSetDelayAfterPDT&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;Spix-&amp;gt;CTAR[0] |= SPI_CTAR_PDT(0x00);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; //For DMA request&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Spix-&amp;gt;RSER |=&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;(SPI_RSER_TFFF_RE_MASK|SPI_RSER_TFFF_DIRS_MASK|SPI_RSER_RFDF_RE_MASK|SPI_RS&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;ER_RFDF_DIRS_MASK);&lt;/P&gt;&lt;P&gt;//SPI config completes here&lt;/P&gt;&lt;P&gt;//DMAMUX configuration&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Enable clock for DMA multiplexer&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; SIM-&amp;gt;SCGC6 |= SIM_SCGC6_DMAMUX_MASK;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;//Enable clock for DMA&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;SIM-&amp;gt;SCGC7 |= SIM_SCGC7_DMA_MASK;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; DMAMUX-&amp;gt;CHCFG[0] |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(39);&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; DMAMUX-&amp;gt;CHCFG[1] |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(38);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;//DMA Transmit config&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; //source address&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[0].SADDR = (uint32_t)spi_buff;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* Source offset disabled */&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].SOFF = 0x00;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].DOFF = 0x00;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].SLAST = 0x00;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Source data transfer size and Destination data transfer size&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].ATTR = DMA_ATTR_SSIZE(0x00)|DMA_ATTR_DSIZE(0x00);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[0].NBYTES_MLNO= 0x01;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; //stop the DMA activity once the single buffer transfer completes&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[0].CSR |= DMA_CSR_DREQ_MASK;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; //Destination address&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;// SPI0-&amp;gt;0x4002C034, SPI1-&amp;gt;0x4002D034, SPI2-&amp;gt;0x400AC034 Push register address&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[0].DADDR =0x400AC034;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* No adjustment to destination address */&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].DLAST_SGA = 0x00;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Current Major Iteration Count&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(1);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; //Starting Major Iteration Count&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(1);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Set enable request&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;SERQ |= DMA_SERQ_SERQ_MASK;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Channel Start&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[0].CSR = DMA_CSR_START_MASK;&lt;/P&gt;&lt;P&gt;//DMA transmit ends here&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;//DMA Receive Starts&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//source address&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; //SPI0-&amp;gt;0x4002C038, SPI1-&amp;gt;0x4002D038, SPI2-&amp;gt;0x400AC038 POP register&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].SADDR = 0x400AC038;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/* Source offset disabled */&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[1].SOFF = 0x00;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].DOFF = 0x00;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].SLAST = 0x00;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; //Source data transfer size and Destination data transfer size&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[1].ATTR = DMA_ATTR_SSIZE(0x00)|DMA_ATTR_DSIZE(0x00);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[1].NBYTES_MLNO= 0x01;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;//stop the DMA activity once the single buffer transfer completes&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].CSR |= DMA_CSR_DREQ_MASK;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;//Destination address&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;// SPI0-&amp;gt;0x4002C034, SPI1-&amp;gt;0x4002D034, SPI2-&amp;gt;0x400AC034 Push register address&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].DADDR =(uint32_t)spi_buff;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; /* No adjustment to destination address */&lt;BR /&gt;&amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[1].DLAST_SGA = 0x00;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Current Major Iteration Count&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(1);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;//Starting Major Iteration Count&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;TCD[1].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(1);&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; //Set enable request&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; DMA0-&amp;gt;SERQ |= DMA_SERQ_SERQ_MASK;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;//Channel Start&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;DMA0-&amp;gt;TCD[1].CSR = DMA_CSR_START_MASK;&lt;/P&gt;&lt;P&gt;//DMA receive ends here&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 30 Oct 2020 06:47:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1175697#M58678</guid>
      <dc:creator>mdrasool_yadwad</dc:creator>
      <dc:date>2020-10-30T06:47:56Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA K66</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1177490#M58715</link>
      <description>&lt;P&gt;Hello &lt;A id="link_12" href="https://community.nxp.com/t5/user/viewprofilepage/user-id/94019" target="_self"&gt;mdrasool_yadwad&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I suggest you to use these documents as a reference to make the SPI and DMA work: &lt;A href="https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-the-DMA-module-in-Kinetis-Devices/ta-p/1107248" target="_blank"&gt;https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-the-DMA-module-in-Kinetis-Devices/ta-p/1107248&lt;/A&gt;. Also I suggest you use the SDK examples of DSPI with DMA.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Let me know if this is helpful, if you have more questions do not hesitate to ask me.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Omar&lt;/P&gt;</description>
      <pubDate>Tue, 03 Nov 2020 18:44:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1177490#M58715</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2020-11-03T18:44:55Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA K66</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1177670#M58723</link>
      <description>&lt;P&gt;The problem I am facing is after triggering the DMA the data is loading into push register but after completion of transfer the TCF bit is setted which is not cleared automatically when i use DMA&lt;/P&gt;</description>
      <pubDate>Wed, 04 Nov 2020 04:32:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1177670#M58723</guid>
      <dc:creator>mdrasool_yadwad</dc:creator>
      <dc:date>2020-11-04T04:32:36Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA K66</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1180997#M58778</link>
      <description>&lt;P&gt;Hello&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The TCF field is cleared writing a 1 to it. Once it is set it is not cleared until 1 is written to it.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Let me know if this is helpful, if you have more questions do not hesitate to ask me.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Omar&lt;/P&gt;</description>
      <pubDate>Tue, 10 Nov 2020 20:48:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1180997#M58778</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2020-11-10T20:48:06Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA K66</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1181196#M58785</link>
      <description>&lt;P&gt;then what is the use of using DMA. For every byte we send using DMA we have to clear the TCF. but when we send 10 bytes using DMA how to clear the TCF.&lt;/P&gt;</description>
      <pubDate>Wed, 11 Nov 2020 04:10:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-DMA-K66/m-p/1181196#M58785</guid>
      <dc:creator>mdrasool_yadwad</dc:creator>
      <dc:date>2020-11-11T04:10:43Z</dc:date>
    </item>
  </channel>
</rss>

