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    <title>topic Re: IEC 60730 RAM test backup area in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1173240#M58614</link>
    <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/179077"&gt;@MLapaj&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I have received feedback on the matter.&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;The backup memory&amp;nbsp; should not&amp;nbsp;be placed inside of tested SRAM memory range. &lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Our suggestion to test all the SRAM range is to create a least&amp;nbsp;two test interfaces, where the backup memory (for the first instance) will be placed in the second instance&amp;nbsp;memory range and vice versa.&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Thank you for your patience.&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Regards,&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Diego&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 26 Oct 2020 15:55:16 GMT</pubDate>
    <dc:creator>diego_charles</dc:creator>
    <dc:date>2020-10-26T15:55:16Z</dc:date>
    <item>
      <title>IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1167353#M58493</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I've got a question regarding RAM test functions from IEC60730 4.0 library for Cortex-M0+.&lt;/P&gt;&lt;P&gt;While using&amp;nbsp;FS_CM0_RAM_AfterReset() and&amp;nbsp;FS_CM0_RAM_Runtime() functions, can the tested memory area include the RAM test backup area or does the backup have to be excluded from tested addresses?&lt;/P&gt;&lt;P&gt;Let's suppose the tesed area is from&amp;nbsp;0x1FFFF000 to&amp;nbsp;0x20002FFF, which is the whole RAM area. Can the backup area overlap with tested area (e.g. can the backup area be placed at&amp;nbsp;0x1FFFF800 address, as long as it is reserved)?&lt;/P&gt;</description>
      <pubDate>Wed, 14 Oct 2020 09:24:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1167353#M58493</guid>
      <dc:creator>MLapaj</dc:creator>
      <dc:date>2020-10-14T09:24:58Z</dc:date>
    </item>
    <item>
      <title>Re: IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1169147#M58534</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/179077"&gt;@MLapaj&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;If the backup memory is inside the tested memory (ovelap),&amp;nbsp; the tests functions&amp;nbsp;&amp;nbsp; probably&amp;nbsp; destroy the contents stored in the backup area for a certain block on a certain&amp;nbsp; in a iteration.&amp;nbsp; I will recommend to avoid overlapping.&lt;/P&gt;
&lt;P&gt;Br,&lt;/P&gt;
&lt;P&gt;Diego.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 17 Oct 2020 18:29:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1169147#M58534</guid>
      <dc:creator>diego_charles</dc:creator>
      <dc:date>2020-10-17T18:29:47Z</dc:date>
    </item>
    <item>
      <title>Re: IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1169399#M58536</link>
      <description>&lt;P&gt;I don't mind the backup area contents being destroyed since it's reserved area anyway. What I am worried about is receiving false negative result of a test. Is there any chance of that happening?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Or are there any other&amp;nbsp;consequences to test area and backup area overlapping?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 19 Oct 2020 07:46:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1169399#M58536</guid>
      <dc:creator>MLapaj</dc:creator>
      <dc:date>2020-10-19T07:46:37Z</dc:date>
    </item>
    <item>
      <title>Re: IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1170510#M58559</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/179077"&gt;@MLapaj&lt;/a&gt; ,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;I will consult&amp;nbsp; internally&amp;nbsp; to validate my reply to your inquiry. Could you let me know&amp;nbsp; the MCU that you are plannig to use with the library?&lt;/P&gt;
&lt;P&gt;Thank you,&lt;/P&gt;
&lt;P&gt;Diego.&lt;/P&gt;</description>
      <pubDate>Tue, 20 Oct 2020 18:43:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1170510#M58559</guid>
      <dc:creator>diego_charles</dc:creator>
      <dc:date>2020-10-20T18:43:05Z</dc:date>
    </item>
    <item>
      <title>Re: IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1170783#M58564</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/89833"&gt;@diego_charles&lt;/a&gt;,&amp;nbsp;&lt;/P&gt;&lt;P&gt;It's being used only on Kinetis KE06 at the time.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 21 Oct 2020 07:07:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1170783#M58564</guid>
      <dc:creator>MLapaj</dc:creator>
      <dc:date>2020-10-21T07:07:11Z</dc:date>
    </item>
    <item>
      <title>Re: IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1173240#M58614</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/179077"&gt;@MLapaj&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I have received feedback on the matter.&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;The backup memory&amp;nbsp; should not&amp;nbsp;be placed inside of tested SRAM memory range. &lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Our suggestion to test all the SRAM range is to create a least&amp;nbsp;two test interfaces, where the backup memory (for the first instance) will be placed in the second instance&amp;nbsp;memory range and vice versa.&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Thank you for your patience.&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Regards,&lt;/P&gt;
&lt;P style="text-align: justify;"&gt;Diego&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 26 Oct 2020 15:55:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1173240#M58614</guid>
      <dc:creator>diego_charles</dc:creator>
      <dc:date>2020-10-26T15:55:16Z</dc:date>
    </item>
    <item>
      <title>Re: IEC 60730 RAM test backup area</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1173615#M58627</link>
      <description>&lt;P&gt;I understand. Thank you for your help.&lt;/P&gt;</description>
      <pubDate>Tue, 27 Oct 2020 07:11:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/IEC-60730-RAM-test-backup-area/m-p/1173615#M58627</guid>
      <dc:creator>MLapaj</dc:creator>
      <dc:date>2020-10-27T07:11:59Z</dc:date>
    </item>
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