Kinetis MicrocontrollersのトピックRe: ERROR: Can not read register 20 (CFBP) while CPU is running

ERROR: Can not read register 20 (CFBP) while CPU is running

723679104 — Tue, 26 Nov 2019 02:57:28 GMT

I debugg MCU MKL26Z256 ,that error disaply , ERROR: CPU is not halted ,ERROR: Can not read register 20 (CFBP) while CPU is running, but I use SEGGER JFLASH can connect MCU , and don't earse and program. info as below:

Application log started
- J-Flash V6.44h (J-Flash compiled May 3 2019 17:37:36)
- JLinkARM.dll V6.44h (DLL compiled May 3 2019 17:37:09)
Opening project file [C:\Users\Sam Huang\AppData\Roaming\SEGGER\Default.jflash] ...
- Project opened successfully
Opening data file [C:\Users\Sam Huang\Desktop\J-FLASH 直接下载文件\snake.hex] ...
- Data file opened successfully (262144 bytes, 1 range, CRC of data = 0x4DDE49BC, CRC of file = 0x45F173CF)
Connecting ...
- Connecting via USB to J-Link device 0
- ERROR: Cannot connect to J-Link via USB.
- ERROR: Failed to connect.
Could not establish a connection to the J-Link.
Connecting ...
- Connecting via USB to J-Link device 0
- J-Link firmware: J-Link ARM-OB STM32 compiled Aug 22 2012 19:52:04
- Device "MKL26Z256XXX4" selected.
- ConfigTargetSettings() start
- ConfigTargetSettings() end
- InitTarget() start
- InitTarget()
- Timeout while halting CPU.
- InitTarget() end
- Found SW-DP with ID 0x0BC11477
- AP map detection skipped. Manually configured AP map found.
- AP[0]: AHB-AP (IDR: Not set)
- AP[1]: CUSTOM-AP (IDR: Not set)
- AP[0]: Core found
- AP[0]: AHB-AP ROM base: 0xF0002000
- CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
- Found Cortex-M0 r0p0, Little endian.
- FPUnit: 2 code (BP) slots and 0 literal slots
- CoreSight components:
- ROMTbl[0] @ F0002000
- ROMTbl[0][0]: F0000000, CID: B105900D, PID: 000BB932 MTB-M0+
- ROMTbl[0][1]: F0001000, CID: B105900D, PID: 0008E000 MTBDWT
- ROMTbl[0][2]: E00FF000, CID: B105100D, PID: 000BB4C0 ROM Table
- ROMTbl[1] @ E00FF000
- ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
- ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
- ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
- Target interface speed: 2000 kHz (Auto)
- VTarget = 3.300V
- ConfigTargetSettings() start
- ConfigTargetSettings() end
- InitTarget() start
- InitTarget()
- Timeout while halting CPU.
- InitTarget() end
- Found SW-DP with ID 0x0BC11477
- AP map detection skipped. Manually configured AP map found.
- AP[0]: AHB-AP (IDR: Not set)
- AP[1]: CUSTOM-AP (IDR: Not set)
- AP[0]: Core found
- AP[0]: AHB-AP ROM base: 0xF0002000
- CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
- Found Cortex-M0 r0p0, Little endian.
- FPUnit: 2 code (BP) slots and 0 literal slots
- CoreSight components:
- ROMTbl[0] @ F0002000
- ROMTbl[0][0]: F0000000, CID: B105900D, PID: 000BB932 MTB-M0+
- ROMTbl[0][1]: F0001000, CID: B105900D, PID: 0008E000 MTBDWT
- ROMTbl[0][2]: E00FF000, CID: B105100D, PID: 000BB4C0 ROM Table
- ROMTbl[1] @ E00FF000
- ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
- ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
- ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
- Executing init sequence ...
- Initialized successfully
- Target interface speed: 2000 kHz (Auto)
- J-Link found 1 JTAG device. Core ID: 0x0BC11477 (None)
- Connected successfully
Erasing chip ...
- 256 sectors, 1 range, 0x0 - 0x3FFFF
- Start of preparing flash programming
- ERROR: Can not read register 20 (CFBP) while CPU is running
- ERROR: CPU is not halted
- CPU could not be halted
- ERROR: Can not read register 15 (R15) while CPU is running
- ERROR: Can not read register 16 (XPSR) while CPU is running
- ERROR: Can not read register 13 (R13) while CPU is running
- ERROR: Timeout while checking target RAM, core does not stop. (PC = 0x00000000, XPSR = 0x00000000, SP = 0x00000000)!
- ERROR: Failed to prepare for programming.
Failed to execute RAMCode for RAM check!
- End of preparing flash programming
- Start of restoring
- End of restoring
- ERROR: Failed to erase chip

Re: ERROR: Can not read register 20 (CFBP) while CPU is running

723679104 — Tue, 26 Nov 2019 04:16:45 GMT

ROMTbl[0][0]: F0000000, CID: B105900D, PID: 000BB932 MTB-M0+
ROMTbl[0][1]: F0001000, CID: B105900D, PID: 0008E000 MTBDWT
ROMTbl[0][2]: E00FF000, CID: B105100D, PID: 000BB4C0 ROM Table
ROMTbl[1] @ E00FF000
ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
Cortex-M0 identified.
J-Link>unlock kinetis
Found SWD-DP with ID 0x0BC11477
Unlocking device...Timeout while unlocking device.
J-Link>unlock kinetis
Found SWD-DP with ID 0x0BC11477
Unlocking device...Timeout while unlocking device.
J-Link>unlock kinetis
Found SWD-DP with ID 0x0BC11477
Unlocking device...Timeout while unlocking device.
J-Link>unlock kinetis
Found SWD-DP with ID 0x0BC11477
Unlocking device...Timeout while unlocking device.

-- and can't unlock device yet.

Re: ERROR: Can not read register 20 (CFBP) while CPU is running

jingpan — Wed, 27 Nov 2019 02:55:53 GMT

Hi,

Sometimes the lock issue is not only caused by software setting, but also hardware problem. Please refer to these documents. If you have tried all the way in these files and still can't work, you have to change a chip.

Regards,

Jing

Re: ERROR: Can not read register 20 (CFBP) while CPU is running

723679104 — Thu, 28 Nov 2019 04:05:51 GMT

thanks

can't ok acorrding your method, details as below

C:\Program Files (x86)\SEGGER\JLink_V644h>jlink.exe erase_all_pin.jlk
SEGGER J-Link Commander V6.44h (Compiled May 3 2019 17:37:48)
DLL version V6.44h, compiled May 3 2019 17:37:09

J-Link Command File read successfully.
Processing script file...

J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: J-Link ARM-OB STM32 compiled Aug 22 2012 19:52:04
Hardware version: V7.00
S/N: 20090937
License(s): RDI,FlashDL,FlashBP,JFlash,GDBFull
VTref=3.300V
Selecting 1000 kHz as target interface speed

Sleep(10)

Target connection not established yet but required for command.
Please specify device / core. <Default>: MKL26Z256XXX4
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>S
Device "MKL26Z256XXX4" selected.

Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end
InitTarget() start
InitTarget()
Timeout while halting CPU.
InitTarget() end
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[1]: CUSTOM-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0002000
CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.
FPUnit: 2 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ F0002000
ROMTbl[0][0]: F0000000, CID: B105900D, PID: 000BB932 MTB-M0+
ROMTbl[0][1]: F0001000, CID: B105900D, PID: 0008E000 MTBDWT
ROMTbl[0][2]: E00FF000, CID: B105100D, PID: 000BB4C0 ROM Table
ROMTbl[1] @ E00FF000
ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
Cortex-M0 identified.
Reset type RESETPIN: Resets core & peripherals using RESET pin.

Reset delay: 0 ms
Reset type RESETPIN: Resets core & peripherals using RESET pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[1]: CUSTOM-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0002000
CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.

**************************
WARNING: CPU could not be halted
**************************

Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[1]: CUSTOM-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0002000
CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.

**************************
WARNING: CPU could not be halted
**************************

Reset: Failed. Toggling reset pin and trying reset strategy again.
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[1]: CUSTOM-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0002000
CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[1]: CUSTOM-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0002000
CPUID register: 0x410CC600. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.

**************************
WARNING: CPU could not be halted
**************************

Sleep(1000)

Disconnecting from J-Link...O.K.
Selecting SWD as current target interface.
Device "MKL26Z256XXX4" selected.

Sleep(10)

Select SWD by sending SWD switching sequence.
Found SWD-DP with ID 0x0BC11477

Sleep(10)

Write DP register 2 = 0x01000000

Sleep(10)

Read AP register 0 = 0x00000000

Sleep(10)

Read AP register 0 = 0x00000030

Sleep(10)

Read AP register 1 = 0x00000030

Sleep(10)

Read AP register 1 = 0x00000004

Sleep(10)

Read AP register 0 = 0x00000004

Sleep(10)

Read AP register 0 = 0x00000030

Sleep(10)

Write AP register 1 = 0x00000001

Sleep(1000)

Read AP register 0 = 0x00000001

Sleep(10)

Read AP register 0 = 0x00000030

Sleep(10)

Read AP register 1 = 0x00000030

Sleep(10)

Read AP register 1 = 0x00000001

Sleep(100)

Write DP register 2 = 0x00000000

Sleep(1000)

Disconnecting from J-Link...O.K.
Selecting JTAG as current target interface.
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Device "MKL26Z256XXX4" selected.

Connecting to target via JTAG
ConfigTargetSettings() start
ConfigTargetSettings() end
InitTarget() start
InitTarget()
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constan

Re: ERROR: Can not read register 20 (CFBP) while CPU is running

jingpan — Fri, 29 Nov 2019 02:50:52 GMT

Hi,

If you have tried all the way, hardware and software, then you have to change a chip.

Regards,
Jing