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    <title>topic FTM0 PWM on MK20DX256 in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM0-PWM-on-MK20DX256/m-p/1032343#M56570</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm using a Teensy 3.1 with MK20DX256 MCU.&lt;/P&gt;&lt;P&gt;I'm writing to the metal (not using Teensy libraries).&lt;/P&gt;&lt;P&gt;I can't seem to get PWM working. I think I need a basic example for FTM0. My code below.&amp;nbsp;&lt;/P&gt;&lt;P&gt;TIA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My init code for the FTM0:&lt;/P&gt;&lt;P&gt;#define PWM_PERIOD 10000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;SIM_SCGC6 |= SIM_SCGC6_FTM0; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// clock to flex timer 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_SC&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// stop clocking the counter&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;dummy = FTM0_FMS;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;// enable write to all FTM registers&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_MODE&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= FTM_MODE_WPDIS; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// disable write protection&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_MODE&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= FTM_MODE_WPDIS | FTM_MODE_FTMEN;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_PWMLOAD = 0x02ff;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;// enable loading of compare values for every channel&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_CNTIN &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// counter initial value&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_CNT &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= 0; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// counter&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_MOD &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= PWM_PERIOD - 1;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// wrap value ie counter modulo&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_SC&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= 0x08;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;// no ISR, up-count, enabled system clock, prescale=1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To enable a particular pin, this code is called:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;&lt;SPAN class=""&gt;switch&lt;/SPAN&gt;(pin)&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;{&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC1:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR1&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// FTM0, teensy 22&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000002;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C0SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC2:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR2&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 23&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000004;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C1SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC3:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR3&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;9&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000008;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C2SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC4:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR4&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 10&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000010;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C3SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD4:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR4&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;6&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000010;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C4SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD5:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;//&lt;SPAN class=""&gt;&amp;nbsp; &lt;SPAN class=""&gt; &lt;/SPAN&gt;&lt;/SPAN&gt;uA_tx('E');&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR5&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 20&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000020;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C5SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD6:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR6&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 21&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000040;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C6SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD7:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR7&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;5&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000080;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C7SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;}&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;To set PWM duty cycle value using a 16 bit variable value:&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;switch&lt;/SPAN&gt;(pin)&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;{&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC1:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C0V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// FTM0, teensy 22 pin 44&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC2:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C1V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 23 pin 45&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC3:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C2V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;9&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC4:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C3V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 10&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD4:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C4V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;6&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt;&lt;SPAN class=""&gt; PTD5:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C5V = value; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;&lt;SPAN class=""&gt;;&lt;/SPAN&gt;//uA_tx('V');break; // &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 20 pin 62&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD6:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C6V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 21 pin 63&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD7:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C7V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;5&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;}&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 30 Mar 2020 01:28:55 GMT</pubDate>
    <dc:creator>DustyStew</dc:creator>
    <dc:date>2020-03-30T01:28:55Z</dc:date>
    <item>
      <title>FTM0 PWM on MK20DX256</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM0-PWM-on-MK20DX256/m-p/1032343#M56570</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm using a Teensy 3.1 with MK20DX256 MCU.&lt;/P&gt;&lt;P&gt;I'm writing to the metal (not using Teensy libraries).&lt;/P&gt;&lt;P&gt;I can't seem to get PWM working. I think I need a basic example for FTM0. My code below.&amp;nbsp;&lt;/P&gt;&lt;P&gt;TIA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My init code for the FTM0:&lt;/P&gt;&lt;P&gt;#define PWM_PERIOD 10000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;SIM_SCGC6 |= SIM_SCGC6_FTM0; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// clock to flex timer 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_SC&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// stop clocking the counter&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;dummy = FTM0_FMS;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;// enable write to all FTM registers&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_MODE&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= FTM_MODE_WPDIS; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// disable write protection&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_MODE&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= FTM_MODE_WPDIS | FTM_MODE_FTMEN;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_PWMLOAD = 0x02ff;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;// enable loading of compare values for every channel&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_CNTIN &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// counter initial value&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_CNT &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= 0; &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// counter&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_MOD &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= PWM_PERIOD - 1;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;// wrap value ie counter modulo&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_SC&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;= 0x08;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;// no ISR, up-count, enabled system clock, prescale=1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To enable a particular pin, this code is called:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;&lt;SPAN class=""&gt;switch&lt;/SPAN&gt;(pin)&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;{&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC1:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR1&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// FTM0, teensy 22&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000002;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C0SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC2:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR2&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 23&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000004;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C1SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC3:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR3&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;9&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000008;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C2SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC4:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTC_PCR4&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 10&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOC_PDDR |= 0x00000010;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C3SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD4:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR4&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;6&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000010;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C4SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD5:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;//&lt;SPAN class=""&gt;&amp;nbsp; &lt;SPAN class=""&gt; &lt;/SPAN&gt;&lt;/SPAN&gt;uA_tx('E');&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR5&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 20&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000020;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C5SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD6:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR6&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 21&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000040;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C6SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD7:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;PORTD_PCR7&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= (uint32_t)(PORT_PCR_MUX(4)); &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;5&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;GPIOD_PDDR |= 0x00000080;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;FTM0_C7SC &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= 0x28;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;}&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;To set PWM duty cycle value using a 16 bit variable value:&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;switch&lt;/SPAN&gt;(pin)&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;{&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC1:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C0V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// FTM0, teensy 22 pin 44&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC2:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C1V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 23 pin 45&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC3:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C2V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;9&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTC4:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C3V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 10&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD4:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C4V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;6&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt;&lt;SPAN class=""&gt; PTD5:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C5V = value; &lt;/SPAN&gt;&lt;SPAN class=""&gt;break&lt;/SPAN&gt;&lt;SPAN class=""&gt;;&lt;/SPAN&gt;//uA_tx('V');break; // &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 20 pin 62&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD6:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C6V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy 21 pin 63&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN class=""&gt;case&lt;/SPAN&gt; PTD7:&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;FTM0_C7V = value; &lt;SPAN class=""&gt;break&lt;/SPAN&gt;; &lt;SPAN class=""&gt;// &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;teensy&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;5&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;}&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Mar 2020 01:28:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM0-PWM-on-MK20DX256/m-p/1032343#M56570</guid>
      <dc:creator>DustyStew</dc:creator>
      <dc:date>2020-03-30T01:28:55Z</dc:date>
    </item>
    <item>
      <title>Re: FTM0 PWM on MK20DX256</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM0-PWM-on-MK20DX256/m-p/1032344#M56571</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Thomas,&lt;/P&gt;&lt;P&gt;I tested your code. It has no problem in register setting. It only need to put duty setting and pin selection code before start.&lt;/P&gt;&lt;P&gt;It should looks like&lt;/P&gt;&lt;P&gt;PWM_Pin_sel(PTD7);&amp;nbsp; &amp;nbsp; &amp;nbsp;//your second function&lt;BR /&gt; PWM_duty(PTD7,PWM_PERIOD/2);&amp;nbsp; &amp;nbsp;// third function&lt;BR /&gt; FTM0_SC = 0x08;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;K20 72M version hasn't SDK. But K20 100M device has. The SDK has lots of FTM example. Since FTM module is same, you can refer to those example.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jing&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Apr 2020 09:41:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/FTM0-PWM-on-MK20DX256/m-p/1032344#M56571</guid>
      <dc:creator>jingpan</dc:creator>
      <dc:date>2020-04-01T09:41:06Z</dc:date>
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