How many clock cycle is required for a read/write operation in K66 controllers

sarath_gs — Thu, 23 Jan 2020 04:02:17 GMT

May i know how many clock cycle is required for a read/write operation in K66 controllers . i need to know flex bus read write speed please help me to find.

Re: How many clock cycle is required for a read/write operation in K66 controllers

diego_charles — Tue, 28 Jan 2020 23:25:24 GMT

Hello, Sarath G

The chapter 3.2.4 Performance calculation of AN4393 Using FlexBus Interface for Kinetis provides an example for the Flex bus maximum throughput, doing an In 8-bit non-muxed mode transfer and requiring 6 cycles, four cycles for transfer and two for wait state cycles:

In this example, the theoretical maximal throughput is the following.
If you run the bus at 50 Mhz, with transfer cycles taking four cycles plus two wait state cycles. In 8-bit non-muxed mode you can transfer eight bits in 6 cycles, therefore eight bits in 120 ns. This translates to 66.6 Mbit / sec.

As the K66 Sub-Family Reference Manual states in chapter 34.5.11.4 Timing Variations the Flexbus has several variations that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data.

In example Wait states can give the peripheral or memory more time to return read data or

sample write data.

According to the AN4393 Using FlexBus Interface for Kinetis The FlexBus read and write cycles have almost the same timing.

From the K66 Sub-Family Reference Manual, both Figure 34-14 and Figure 34-15 illustrates the basic read-bus and write diagrams with no wait states.

In the Figure Figure 34-22, you could see that a write cycle requires up to seven clock cycles using the address setup, a wait state

and the address hold. In the Figure 34-23. eighth bus cycles are required to perform a 32 bit read burst.

In conclusion, the required cycles used by the read and write operation may depend on wait states, address setup, address hold time, bit transfer size and if burst mode is being used.

Have a great day,
Diego

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Kinetis MicrocontrollersのトピックHow many clock cycle is required for a read/write operation in K66 controllers

How many clock cycle is required for a read/write operation in K66 controllers

Re: How many clock cycle is required for a read/write operation in K66 controllers