topic Re: Clock jitter in Kinetis Microcontrollers

Clock jitter

smathad — Thu, 06 Feb 2020 13:05:07 GMT

Hello NXP community,

We are currently working on Kinetis K24. We want to replace the clock source of 8MHz crystal oscillator with the in-built 48MIRC internal oscillator in our systems. We are generating PLL based 120MHz core clock in our system.

This provision is provided by nxp and procedure has been described in the reference manual.

My questions are:

1. How do we calculate the jitters/error rate of this new clock, both theoretically and practically?

2. Has anybody run their system on the 48MIRC with stability? We want the system to be stable in -40C to 85C temperature ranges.

Regards,

Sachin

Re: Clock jitter

diego_charles — Fri, 07 Feb 2020 22:48:39 GMT

Hello, Sachin

How do we calculate the jitters/error rate of this new clock, both theoretically and practically?

About the IRC48M jitter, there are two cases to consider.

1 Bypassing the PLL to use the IRC48M directly.

IRC48M Typical frequency deviation of ± 0.5 %f_IRC48M,
IRC48M Period Jitter (RMS) Max. 150 ps.
Note: these values are applicable under all temperature ranges.

2 Using the IRC48M and the PLL.

PLL period jitter (RMS) 120 ps
PLL accumulated jitter over 1μs (RMS) 1350 ps

Note: In the worst-case scenario the IRC deviation and jitter can be added to PLL output.

Please refer to Table 15. MCG specifications and Table 18. IRC48M specifications of your

Device Data Sheet.

Has anybody run their system on the 48MIRC with stability? We want the system to be stable in -40C to 85C temperature ranges.

All the devices will meet the specification if they are used under the spec condition, because of this the 48IRCM and PLL clock is under the jitter specifications mentioned above. The K24 Temperature range (°C) field is C (–40 to 85 °C) or V (–40 to 105 °C) can work at -40C without any problem, please refer to your device datasheet chapter Fields,

Please note that the specifications that datasheet provides were obtained using an NXP developed PCB. The PLL jitter is dependent on the noise characteristics of each PCB and results will vary.

Please let me know if you need further support.

Have a great day,
Diego

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Re: Clock jitter

smathad — Mon, 10 Feb 2020 06:14:03 GMT

Hi Charles,

Thank you for your response.

Can you recommend some practical methods to calculate jitter?

Regards,

Sachin

Re: Clock jitter

diego_charles — Mon, 10 Feb 2020 21:10:41 GMT

Hello, smathad@hubbell.com

To do your own measurements you can output by CLKOUT pin of the MCU the desired

The clock signal to measure (IRC48M, PLL_CLK ). But you will need to take into account that the GPIO

Pin used for the output and other Hardware modules, PLL loop noise, thermal noise, cross talk, power supply ripple,

could add error to the clock signal.

Also from, the NXP documentation I could recommend you to take a look at the following Application note

Understanding SYSCLK Jitter Although the document is intended for Power Quick processors

it provides a brief overview of the basic terminology of jitter.

If you need further assistance for the configuration of the CLKOUT pin. Please let me know.

Have a great day,
Diego

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