topic MKE18F Flash & SRAM ECC in Kinetis Microcontrollers

MKE18F Flash & SRAM ECC

divya_kapu — Fri, 13 Dec 2019 08:48:33 GMT

From the MKE18F512VLH16 RM I understand there is Error-correcting code (ECC) on Flash and SRAM memories.
For flash, I could not find any register to enable/disable ECC. Is ECC enabled for flash by default?
I could force double bit error in flash by setting FDFD bit in FTFE_FERCNFG and verify that double
bit fault interrupt flag DFDIF bit in FTFE_FERSTAT is set. I wanted to understand is there any such similar way to force double bit error for SRAM? Under MCM interface in MCM_LMDR register, CF0 field provides capability for ECC Enable Read Check and ECC Enable Write Generation for TCM (couldnt find much documentation on TCM). By setting CF0[0] to 0 can we disable EEWG for SRAM? I have set ERNCR in MCM_LMPECR register to report RAM non correctable error. Can we force ECC non correctable fault in SRAM and verify that ENC field of MCM_LMPEIR set? Also, do MKE18F512VLH16 has any self test capabilities?

Re: MKE18F Flash & SRAM ECC

FelipeGarcia — Tue, 17 Dec 2019 15:21:00 GMT

Hello Divya,

The multiple-bit fault is enabled using the FERCNFG[DFDIE] bit. When the multiple-bit error is detected, the FERSTAT[DFDIF] flag is set, and the interrupt request is generated.

Regarding your other questions:

By setting CF0[0] to 0 can we disable EEWG for SRAM?

Yes.

Can we force ECC non correctable fault in SRAM and verify that ENC field of MCM_LMPEIR set?

Yes, but you will need to enable MCM_LMPECR[ERNCR] to enable reporting this error.

MKE18F512VLH16 has any self test capabilities?

Could you please provide more details about this, I don’t know exactly what you mean.

I hope this helps!

Best regards,

Felipe

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Re: MKE18F Flash & SRAM ECC

divya_kapu — Thu, 19 Dec 2019 09:18:18 GMT

Hi Felipe,

Thank you for the input. I have enabled the ERNCR error reporting and disabled the EEWG by setting CF[0] to 0x02. Written 32 bit data to the SRAM upper and read the data from same address but could not find the ENC field of MCM_LMPEIR set. Please suggest me a way to force ECC fault in SRAM which sets the ENC field of MCM_LMPEIR.

MCM->LMPECR |= MCM_LMPECR_ERNCR_MASK; /* ECC Noncorrectable error */

MCM->LMDR[1] = MCM_LMDR_CF0(0x2);

*(uint32_t*)0x20000001 = 0xA5A5A5A5;

uint32_t read_sram = *(uint32_t*)0x20000001;

Regards,

Divya

Re: MKE18F Flash & SRAM ECC

FelipeGarcia — Thu, 26 Dec 2019 17:22:09 GMT

Hi Divya,

I am sorry for my late reply. I have checked this with internal team. I was told that it is not possible generate RAM ECC error on purpose, because user can't modify the RAM contents without ECC re-calculation.

Sorry for the inconvenience this may cause you.

Best regards,

Felipe