<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic NMI and PTA4 behaviour? in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961779#M55028</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I just ran into some unexpected behaviour from PTA4 on the FRDM-KL25Z, and hoping someone can help me understand it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I was trying to use PTA4 as a GPIO input with an IRQ handler. I noticed that when PTA4 was triggered the board's processing came to a halt, turns out that PTA4 is hooked up to an NMI interrupt vector which is just looping infinitely (as per the boilerplate code).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm surprised because I had set the MUX bits for that pin to ALT1 yet it seems to have no effect and continues to operate as the NMI (Alt 7).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Firstly, I don't really understand what the NMI does (my guess is that it's just an interrupt that can't be masked by software) and secondly, I can't understand why setting the MUX bits to ALT1 seems to have no impact on this pin.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As an aside, it's somewhat problematic for me, as I've noticed that on this chip / board only Port A and D have interrupts, so I've a limited number of pins I can actually use as interrupt GPIO without disabling other functionality elsewhere.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anyway, if you could help shed some light on my ignorance that'd be appreciated as always.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Paul Swanson&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 10 Jul 2019 00:13:19 GMT</pubDate>
    <dc:creator>q1220200</dc:creator>
    <dc:date>2019-07-10T00:13:19Z</dc:date>
    <item>
      <title>NMI and PTA4 behaviour?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961779#M55028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I just ran into some unexpected behaviour from PTA4 on the FRDM-KL25Z, and hoping someone can help me understand it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I was trying to use PTA4 as a GPIO input with an IRQ handler. I noticed that when PTA4 was triggered the board's processing came to a halt, turns out that PTA4 is hooked up to an NMI interrupt vector which is just looping infinitely (as per the boilerplate code).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm surprised because I had set the MUX bits for that pin to ALT1 yet it seems to have no effect and continues to operate as the NMI (Alt 7).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Firstly, I don't really understand what the NMI does (my guess is that it's just an interrupt that can't be masked by software) and secondly, I can't understand why setting the MUX bits to ALT1 seems to have no impact on this pin.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As an aside, it's somewhat problematic for me, as I've noticed that on this chip / board only Port A and D have interrupts, so I've a limited number of pins I can actually use as interrupt GPIO without disabling other functionality elsewhere.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anyway, if you could help shed some light on my ignorance that'd be appreciated as always.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Paul Swanson&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 10 Jul 2019 00:13:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961779#M55028</guid>
      <dc:creator>q1220200</dc:creator>
      <dc:date>2019-07-10T00:13:19Z</dc:date>
    </item>
    <item>
      <title>Re: NMI and PTA4 behaviour?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961780#M55029</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="341437" data-username="q1220200@umail.usq.edu.au" href="https://community.nxp.com/people/q1220200@umail.usq.edu.au"&gt;Paul Swanson&lt;/A&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; NMI pin is the special pin, if you don't want to use it, you need to disable it from the FOPT.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; FOPT in the flash configuration field, the address is: 0X40D&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/90855iED2F467BB903802C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;If you want to disable the NMI pin function, please configure NMI_DIS bit to 0.&lt;/P&gt;&lt;P&gt;Please try it again on your side.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Kerry&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 10 Jul 2019 08:49:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961780#M55029</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2019-07-10T08:49:19Z</dc:date>
    </item>
    <item>
      <title>Re: NMI and PTA4 behaviour?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961781#M55030</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for your detailed answer, Kerry.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jul 2019 00:14:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961781#M55030</guid>
      <dc:creator>q1220200</dc:creator>
      <dc:date>2019-07-25T00:14:14Z</dc:date>
    </item>
    <item>
      <title>Re: NMI and PTA4 behaviour?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961782#M55031</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp; &lt;A _jive_internal="true" data-content-finding="Community" data-userid="341437" data-username="q1220200@umail.usq.edu.au" href="https://community.nxp.com/people/q1220200@umail.usq.edu.au"&gt;Paul Swanson&lt;/A&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; You are welcome!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; If you have any further questions about it, please let me know.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; If your question is solved, please help me make the correct answer, just to close this case, thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Kerry&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jul 2019 02:11:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/NMI-and-PTA4-behaviour/m-p/961782#M55031</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2019-07-25T02:11:21Z</dc:date>
    </item>
  </channel>
</rss>

