topic Re: How to reduce spikes on VDD when UART TX pin state changes? in Kinetis Microcontrollers

How to reduce spikes on VDD when UART TX pin state changes?

florianpantale1 — Tue, 04 Jun 2019 17:36:24 GMT

Board: FRDM-K22F

Test project: hello_world from SDK demo_apps

Hi,

We have noticed voltage spikes on our project board with Kinetis MK22FN256VLH12, they occur when UART0 TX pin state changes.

I have reproduced the problem when FRDM-K22F demo board and the simple hello_world project.

VDD supply is monitored with a scope trigged by UART1 TX pin state changes. TX pin is PORTE0 for hello_world project.

The spikes can reach 600 mV peak-to-peak with default project settings.

They can be reduced down to 60 mV peak-to-peak when the slew rate is configured to Slow with full pin configuration using PORT_SetPinConfig as shown in attached file.

60 mVpp is still too high if running ADC simultaneously.

Question: are there other settings (hardware and/or software) to further reduce these spikes?

Thanks

Re: How to reduce spikes on VDD when UART TX pin state changes?

Robin_Shen — Wed, 05 Jun 2019 03:13:14 GMT

Hi Florian,

Would you please attach the whole project? So that I can direct test it on FRDM-K22F board.
Seems caused by the circuit design of analog power.

The following analog power supply is widely recommended:

Best Regards,

Robin

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Re: How to reduce spikes on VDD when UART TX pin state changes?

florianpantale1 — Wed, 05 Jun 2019 07:51:34 GMT

Hi Robin,

thanks for quick reply. Please find attached test project.

Best regards,

Re: How to reduce spikes on VDD when UART TX pin state changes?

florianpantale1 — Tue, 11 Jun 2019 08:38:44 GMT

Hi Robin,

any news about this subject? Have you got the same results with attached test project?

Also, please note the question focuses on reducing VDD spikes when UART TX pin changes its state.

VDDA is another topic even if I mention ADC at the end of my question.

Best regards,

Florian

Re: How to reduce spikes on VDD when UART TX pin state changes?

Robin_Shen — Wed, 12 Jun 2019 08:50:00 GMT

Hi Florian,

Get the similar phenomenon on the FRDM-K22F board.

But the spikes are much smaller on TWR-K64F120M and TWR-K70F120M board.

default project settings: 150mV peak-to-peak

slew rate configured: 50mV peak-to-peak

So I think the power circuit design are import and be able to reduce these spikes.

Best Regards,

Robin

Re: How to reduce spikes on VDD when UART TX pin state changes?

florianpantale1 — Wed, 12 Jun 2019 10:46:54 GMT

Hi Robin,

Thanks for comparison with other boards.

I will transmit yours answers to our HW engineers for improvement.

Best regards,

Florian