GPIO Attribute Checker Register

jun1 — Thu, 04 Jul 2019 07:41:32 GMT

Hello
Use the MKM33Z128ACLL5.

Please tell me about 42.2.4 GPIO Attribute Checker Register (GPIOx_GACR) in the KM series reference manual.

This seems to be a feature that restricts port access.
I think that it is a function to limit not to be rewritten carelessly.
So I do not understand this 3-bit explanation well.

Attribute Check Byte
This 3 bit field defines the attributes required to access the corresponding GPIO port's programming model.
000 User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
001 User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
010 User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
011 User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
100 User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
101 User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
110 User nonsecure: None; User Secure: None; Privileged Secure: Read
111 User nonsecure: None; User Secure: None; Privileged Secure: None

User nonsecure, User Secure and Privileged Secure do not know the relationship with specific operations.
(Is there no privilege for KM33 in the first place?)
For example, please tell us what happens if you set 111.
Or please tell us the location of the explanatory document.

Thank you.

jun

Re: GPIO Attribute Checker Register

jingpan — Fri, 05 Jul 2019 08:14:48 GMT

Hi jun,

KM33 has 2 master, M0 core and DMA. Please see the RM page 68, Figure 3-7

The MCM_MATCR0 register control these two masters' attribute(RM page 232).

If you set GPIOx_GACR to 111, then none of these two masters can access this port.

Regards,

Jing

topic Re: GPIO Attribute Checker Register in Kinetis Microcontrollers

GPIO Attribute Checker Register

Re: GPIO Attribute Checker Register