topic Re: About the SRAM locations in KL25Z in Kinetis Microcontrollers

About the SRAM locations in KL25Z

tagerud — Wed, 17 Jul 2019 12:40:03 GMT

When reading the user guide for M0+ (https://static.docs.arm.com/dui0662/a/DUI0662A_cortex_m0p_r0p0_dgug.pdf) on page 22 it says that SRAM starts at address 0x2000_0000. However, in the KL25 reference manual, the SRAM is divided in upper and lower sections, where the lower starts at 0x1FFF_F000 (for my 128 KB device). This would put it in the code section, according to the user guide.

I would just like to understand why this is the case? According to an answer to this question: Why is SRAM split, and what does it mean?, the M0+ does not have separate busses for upper and lower SRAM, so I don't really have to think about it. But even so, why go against the CPU memory model?

Edit: Corrected lower adress.

Re: About the SRAM locations in KL25Z

Alexis_A — Mon, 22 Jul 2019 23:57:45 GMT

Dear tagerud@gmail.com‌,

All the Kinetis Devices has the SRAM memory partitioned this way, in the case of the K series the reason is shown in the next application note (Optimizing performance on Kinetis K-series MCUs AN4745):

All Kinetis K-series devices include two blocks of on-chip SRAM. The first block (SRAM_L) is mapped to the CODE bus, and the second block (SRAM_U) is mapped to the system bus. The memory itself can be accessed in a single cycle, but because instruction accesses to the system bus incurs a one clock delay at the core, SRAM_U instruction accesses take at least two clocks.

And for example in the KL8x, In LLS2 and VLLS2 the 32KB region of SRAM_U based at 0x2000_0000 are powered.

So this is a convention in the Kinetis MCUs.

I hope this information helps you.

Best Regards,

Alexis Andalon

Re: About the SRAM locations in KL25Z

tagerud — Tue, 23 Jul 2019 15:25:57 GMT

That makes perfect sense. Thank you for the source!