topic Re: K65 Allowing for Cache and DMA coherence in Kinetis Microcontrollers

K65 Allowing for Cache and DMA coherence

unknowncoder — Mon, 29 Jul 2019 19:03:12 GMT

Background

I am looking at enabling the code cache controller on the K65 to improve performance.
I utilize DMA for peripheral to memory and memory to peripheral transfer.
I know cache and DMA don't normally work good together and the normal operation is to invalidate the cache before/after, read/write respectively.

Question

From the Table 30-1 it shows that SRAM is non-cacheable. Given this if I make sure that all access with DMA occurs within SRAM would I need to invalidate the cache still?

Thanks

jingpan — Wed, 31 Jul 2019 02:19:35 GMT

Hi,

Yes, you are right. SRAM in K65 is a kind of TCM. Its speed is same as M4 kernel. It needn't cache.

Regards,

Jing

unknowncoder — Wed, 31 Jul 2019 13:10:44 GMT

Are both upper and lower memory tightly coupled memory to the core?

jingpan — Thu, 01 Aug 2019 02:14:13 GMT

Hi,

Yes.

Regards,

Jing