topic Re: The maximum Data transfer at KL1x in Kinetis Microcontrollers

The maximum Data transfer at KL1x

yuriytarnopolsk — Fri, 25 Oct 2013 12:41:38 GMT

Hello! I'm starting to learn Kinetis KL1x General Purpose MCUs, coming from MSP world. For rapid development of Cortex M0+ Core I would like to get answers to the following questions:

What is the maximum data transfer can be achieved when the data going in the external port and when reading from a port? As I understand this speed is equal to the Peripheral Module frequency - 24 MHz. Can I find anywhere Sample code which performs reading the data from the external parallel bus? I am interested in, for example, perform reading a short sequence of data from external parallel 8-bit ADC at 24 MHz and writes it’s to the Kinetis RAM memory. Or as alternative - the realization at Kinetis KL1x synchronous FIFO controller with 24 MHz frequency and volume 2 KB?
Whether DMA may provide a data transfer rate at 24 MHz frequency?
Is it possible to provide 48MHz Kinetis Core frequency when I use a 24 MHz frequency Oscillator crystal or resonator?

Re: The maximum Data transfer at KL1x

perlam_i_au — Tue, 18 Feb 2014 18:11:40 GMT

Hi Yuriy:

Well there is not a something like the example code you mentioned in the product page but you can do it based on the codeWarrior Examples for Kinetis K family (attached).

Regard DMA frequency, you want to know if this module still working with a core or system frequency of 24MHz?? I was not able to understand the question, could you please explain more?

And finally regard 48MHz core frequency using a 24MHz external oscilator source, you can do it, you should configure the MCG module like is depicted below:

1.- The external signal must pass trought the PLL, then as you can read in the field PRDIV0 in MCG Control 5 Register (MCG_C5)

"Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must

be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the

PRDIV 0 value must not be changed when LOCK0 is zero."

Then you should set this field to value 0b01011 which means a divide factor of 12, this will produce a PLL output of a 2MHz signal, which achieve the rule mentioned above.

2.-Now the 2MHz will be multiplied by configuring the VDIV0 field on the MCG Control 6 Register (MCG_C6) to value 0b00000 which means a multiply factor of 24, it produce a 48MHz signal.

3.-This signal will pass trough a last divider, for select devide by 1 the field OUTDIV1 on the System Clock Divider Register 1 (SIM_CLKDIV1) should be set to 0b0000 value.

Cheers,
Perla

-------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-------------------------------------------------------------------------------

Re: The maximum Data transfer at KL1x

yuriytarnopolsk — Fri, 30 May 2014 07:07:16 GMT

Hi Perla!

Thanks for the answer and explanation. This issue has been resolved.