topic Re: kinetis kea ftm0 mode register in Kinetis Microcontrollers

kinetis kea ftm0 mode register

fabrizioborra — Thu, 27 Jun 2019 15:16:54 GMT

I'm using a Kinetis S9KEAZN32AVLC.

I see that FTM0 channel 0 status and control register (FTM0_C0SC) has some bits write protected (MSB MSA ELSB ELSA).

To write these bits the write protect bit must be = 1 (default condition at power on reset) but the MODE register of FTM0 timer doesn't exist.

What is the meaning of a protection bit in a register that doesn't exist?

Thank You.

Re: kinetis kea ftm0 mode register

mjbcswitzerland — Thu, 27 Jun 2019 18:50:36 GMT

In the S9KEAZN32 there is a register FTM0_MODE at the address 0x40038054 with the WPDIS bit - default is '1' according to the user's manual. However, as you probably are aware, the FTMx_MODE is only implemented in FTM2 (and not in FTM0 and FTM1). Therefore you should avoid accessing FTM0_MODE (I think that it will give a hard fault if tried).

Basically it means that the FTM0 and FTM1 have reduced features and so you can't set its registers to write protect mode as you can with FTM2. Therefore - as all FTMs - FTM0 comes up with no write protection and you should not try to protect it since it is not supported.

Regards

Mark

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Re: kinetis kea ftm0 mode register

Robin_Shen — Fri, 28 Jun 2019 02:26:03 GMT

Hi Fabrizio Borra,

You can find the answer in "3.9.1.1 FTM overview" of S9KEA64Z64M20SF0RM.

Best Regards,

Robin

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Re: kinetis kea ftm0 mode register

Omar_Anguiano — Fri, 28 Jun 2019 20:46:29 GMT

Hi Fabrizio

Your answer can be found at the reference manual. You can find the link below.

The image below is the register, you can access though this syntax: FTM0->MODE |= FTM_MODE_WPDIS_MASK;

And here is a brief description of the protection bit:

Reference Manual: https://www.nxp.com/docs/en/reference-manual/KEA8RM.pdf

Greetings

Omar