SRAM Data Retention during VLLS3 Power Mode

iamsaranvs — Sun, 13 Oct 2019 11:42:51 GMT

Hi Team,

I am using MKW40Z160 controller in my project. The controller will initially do all the configurations and it will go into Sleep mode ( VLLS3), Upon button press it will wake from sleep mode and if no other intervention seems to happen within 5 sec it will again go into sleep mode. we will be logging those button press which are meant to wake the controller from sleep mode. I am facing with an issue in logging this count as it doesn't seems to incrementing(i.e,we checked the memory location using IAR Workbench Memory live update, in that the variable will increment once the button is pressed, and once the controller goes to sleep the variable again resets to zero (i.e, the SRAM segment data retention doesn't happen for this updation). we placed the variable 'X' in the address location "0x1ffff75a", the type of variable is static unit8_t. Similarly we have another variable 'Y' placed at location "0x1ffff65c" , the type is unit32_t, no issue with that variable updation, it seems to be working fine. The Updation issue happens only while the system comes from sleep to wake mode(upon button press), once it is in wake mode, then the updation sequence are proper.

Re: SRAM Data Retention during VLLS2 Power Mode

Sebastian_Del_Rio — Mon, 21 Oct 2019 16:10:49 GMT

Hi Saran, I hope you're doing well!

Could you please verify that you are entering VLLS2 and not another VLLSx power mode instead?

To enter VLLS2 mode, the LLSM bits of the SMC_STOPCTRL register should be set to '010', and the STOPM bits in the SMC_PMCTRL should be set to '100'.

Please let me know of your findings.

For more information, could you please take a look at the KW40Z's reference manual, chapter 12, here?

Best regards,

Sebastian

topic SRAM Data Retention during VLLS3 Power Mode in Kinetis Microcontrollers

SRAM Data Retention during VLLS3 Power Mode

Re: SRAM Data Retention during VLLS2 Power Mode