Kinetis MicrocontrollersのトピックRe: DMA read from SDRAM

DMA read from SDRAM

jeff_hane — Mon, 29 Apr 2019 22:28:20 GMT

I am currently using a K28 board to prototype out device. I receive data over USB which is written to a buffer and eventually I use DMA to write this buffer over QSPI to an FPGA. When the buffers are located in SRAM this works fine but I need to add some additional larger buffer. So I enable SDRAM and use buffers allocated there. I can receive the data over USB and by examining the SDRAM I can see the data is written successfully. However, for the DMA from SDRAM to QSPI I never get the DMA complete notification.

Since USB can write to SDRAM I assume SDRAM is configured properly so I'm not sure what to look at. Anyone done this or have any ideas?

thanks,

jeff

Re: DMA read from SDRAM

Alexis_A — Mon, 06 May 2019 18:58:01 GMT

Dear Jeff,

How are you configuring the trigger of the second DMA transmission?

Please check the following post:

https://community.nxp.com/docs/DOC-329561

Here explains how to configure channel linking feature.

Best Regards,
Alexis Andalon

Re: DMA read from SDRAM

jeff_hane — Tue, 07 May 2019 18:44:28 GMT

Hello,

Thanks for you reply but I'm no looking the link the USB directly to the QSPI. There are multiple data sources for the QSPI interface so I have to manage the transactions through a queue so can't have incoming USB packets directly trigger a QSPI access.

Some further info, here is the setup I am using

#define SDRAM_START_ADDRESS (0x70000000U)
#define BUS_CLK_FREQ CLOCK_GetFreq(kCLOCK_FlexBusClk)

uint32_t soptReg;
uint32_t fbReg;

sdramc_refresh_config_t refreshConfig;
sdramc_blockctl_config_t blockConfig;
sdramc_config_t config;
refreshConfig.refreshTime = kSDRAMC_RefreshThreeClocks;
refreshConfig.sdramRefreshRow = 15625;
refreshConfig.busClock_Hz = 60000000;
blockConfig.block = kSDRAMC_Block0;
blockConfig.portSize = kSDRAMC_PortSize16Bit;
blockConfig.location = kSDRAMC_Commandbit19;
blockConfig.latency = kSDRAMC_RefreshThreeClocks;
blockConfig.address = SDRAM_START_ADDRESS;
blockConfig.addressMask = 0x7c0000;
config.refreshConfig = &refreshConfig,
config.blockConfig = &blockConfig,
config.numBlockConfig = 1;

/* Set clock out to flexbus CLKOUT. */
CLOCK_SetClkOutClock(0);

/* Sets the Flexbus security level*/
soptReg = SIM->SOPT2 & ~SIM_SOPT2_FBSL_MASK;
SIM->SOPT2 = soptReg | SIM_SOPT2_FBSL(3);

/* Enable the FB_BE_xx_yy signal in Flexbus */
CLOCK_EnableClock(kCLOCK_Flexbus0);

fbReg = FB->CSPMCR & ~FB_CSPMCR_GROUP2_MASK;
FB->CSPMCR = fbReg | FB_CSPMCR_GROUP2(2);
fbReg = FB->CSPMCR & ~FB_CSPMCR_GROUP3_MASK;
FB->CSPMCR = fbReg | FB_CSPMCR_GROUP3(2);
fbReg = FB->CSPMCR & ~FB_CSPMCR_GROUP4_MASK;
FB->CSPMCR = fbReg | FB_CSPMCR_GROUP4(2);
fbReg = FB->CSPMCR & ~FB_CSPMCR_GROUP5_MASK;
FB->CSPMCR = fbReg | FB_CSPMCR_GROUP5(2);
/* SDRAM initialize. */
SDRAMC_Init(SDRAM, &config);

thanks,

jeff

Re: DMA read from SDRAM

Alexis_A — Thu, 09 May 2019 21:42:56 GMT

Dear Jeff,

Could you check if the transmission alone from the SDRAM to the QSPI is doing it right? Maybe the problem could be in the transmission between this two peripherals.

Best Regards,
Alexis Andalon

Re: DMA read from SDRAM

jeff_hane — Fri, 24 May 2019 21:49:59 GMT

Hi Alex,

Thanks for your response but I wasn't quite clear what you were asking. However, I made me go back and try just doing a small block of data using PIO from SDRAM to QSPI. This appears to work. I wanted to use SDRAM so I could allocate larger buffers of around 100K but after the PIO test I tried testing with smaller buffers. DMA did work for smaller buffers.

After some more digging I discovered that the IDATSZ field in one of the QSPI registers can only go up to 65K. This resulted in there being a difference between the QSPI and the DMA engine so I believe the DMA was hanging because the QSPI was not accepting enough data. Now I just have to figure out how to do large DMAs to QSPI.

thanks,

jeff

Re: DMA read from SDRAM

Alexis_A — Mon, 27 May 2019 19:42:24 GMT

I'm glad that you could resolve your problem and thanks to share your solution.

Best Regards,

Alexis Andaon