topic the system address map of cortex_m4 in Kinetis Microcontrollers https://community.nxp.com/t5/Kinetis-Microcontrollers/the-system-address-map-of-cortex-m4/m-p/890880#M52634 <HTML><HEAD></HEAD><BODY><P>the cortex_m4 technical reference manual say that:from 0x00000000 to 0x20000000 is code map,from 0x20000000 to</P><P>0x40000000 is sram,</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="微信截图_20190513092959.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/79928iEF42F18CBFB791A3/image-size/large?v=v2&amp;px=999" role="button" title="微信截图_20190513092959.png" alt="微信截图_20190513092959.png" /></span></P><P>but the k64&nbsp;<SPAN>&nbsp;technical reference manual say that:the sram map is from 0x1fff0000<span class="lia-inline-image-display-wrapper" image-alt="微信截图_20190513093417.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/70591i709F98DE11C3ACBF/image-size/large?v=v2&amp;px=999" role="button" title="微信截图_20190513093417.png" alt="微信截图_20190513093417.png" /></span></SPAN></P><P><SPAN>why the inital address of sram is in the code map of&nbsp; cortex_m4?</SPAN></P></BODY></HTML> Mon, 13 May 2019 01:39:17 GMT dugg 2019-05-13T01:39:17Z the system address map of cortex_m4 https://community.nxp.com/t5/Kinetis-Microcontrollers/the-system-address-map-of-cortex-m4/m-p/890880#M52634 <HTML><HEAD></HEAD><BODY><P>the cortex_m4 technical reference manual say that:from 0x00000000 to 0x20000000 is code map,from 0x20000000 to</P><P>0x40000000 is sram,</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="微信截图_20190513092959.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/79928iEF42F18CBFB791A3/image-size/large?v=v2&amp;px=999" role="button" title="微信截图_20190513092959.png" alt="微信截图_20190513092959.png" /></span></P><P>but the k64&nbsp;<SPAN>&nbsp;technical reference manual say that:the sram map is from 0x1fff0000<span class="lia-inline-image-display-wrapper" image-alt="微信截图_20190513093417.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/70591i709F98DE11C3ACBF/image-size/large?v=v2&amp;px=999" role="button" title="微信截图_20190513093417.png" alt="微信截图_20190513093417.png" /></span></SPAN></P><P><SPAN>why the inital address of sram is in the code map of&nbsp; cortex_m4?</SPAN></P></BODY></HTML> Mon, 13 May 2019 01:39:17 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/the-system-address-map-of-cortex-m4/m-p/890880#M52634 dugg 2019-05-13T01:39:17Z Re: the system address map of cortex_m4 https://community.nxp.com/t5/Kinetis-Microcontrollers/the-system-address-map-of-cortex-m4/m-p/890881#M52635 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>Yes, Kinetis K series devices split SRAM to two block and two address range. Please refer to 3.5.3.3 SRAM accesses in 64 reference manual. From figure 3-26, you can see that two memory block has their own access port. Thus, CPU core and other masters can access them simultaneously. This structure can speed up its work.</P><P>BTW, it is not recommended to mix use these two block. Please refer to <A class="link-titled" href="https://mcuoneclipse.com/2013/07/10/freertos-heap-with-segmented-kinetis-k-sram/" title="https://mcuoneclipse.com/2013/07/10/freertos-heap-with-segmented-kinetis-k-sram/">FreeRTOS Heap with Segmented Kinetis K SRAM | MCU on Eclipse</A>&nbsp;</P><P></P><P>Regards,</P><P>Jing</P></BODY></HTML> Mon, 13 May 2019 08:45:25 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/the-system-address-map-of-cortex-m4/m-p/890881#M52635 jingpan 2019-05-13T08:45:25Z