Kinetis MicrocontrollersのトピックRe: Kinetis K65 interrupt nesting

Kinetis K65 interrupt nesting

kishorebolisett — Sat, 29 Dec 2018 05:51:53 GMT

I am using one of the PIT channel as a base timer interrupt for my scheduler. Is there a way or workaround to allow the same interrupt to come again when the interrupt is getting executed? I want to implement a task overrun based on this feature. Otherwise please suggest a better way of doing it.

Re: Kinetis K65 interrupt nesting

kerryzhou — Wed, 02 Jan 2019 11:01:17 GMT

Hi Kishore Bolisetti,

What do you mean? Do you still want to use another PIT channel timer interrupt?

From the K65 interrupt vector assignments table, you can know that different PIT channel have different vector

So, you can use other PIT channel interrupt.

But the same interrupt when happens, and didn't exit the ongoing interrupt handler, it can't generate another same interrupt.

So, I think you can try another channel PIT interrupt.

Wish it helps you!

If you still have question about it, please kindly let me know.

Have a great day,
Kerry

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: Kinetis K65 interrupt nesting

mjbcswitzerland — Wed, 02 Jan 2019 18:11:45 GMT

When you are running in the interrupt context the interrupt mask level will be set to the interrupt's priority. If you thus clear the original interrupt in the peripheral and allow it to fire again it won't be able to pre-empt the original interrupt routine unless it has a higher priority.

You could thus increase the interrupt priority of the peripheral in the first interrupt handler to make it able to interrupt again.

Regards

Mark

Complete Solutions and technical support for professional Kinetis developments: http://www.utasker.com/kinetis.html

Re: Kinetis K65 interrupt nesting

kishorebolisett — Sat, 05 Jan 2019 03:49:20 GMT

Hi, Thanks for the response. My configurations are as per below:

1. During Initialization

1.1 Configure PIT channel 2 interrupt (5 milliseconds periodicity)

1.2 Set Priority group in (SCB AIRCR register) to 3

1.3 Set NVIC priority register to have a value of 0x40

1.4 Start the PIT channel

2. In interrupt processing

2.1 Clear PIT Channel 2 status

2.2 Set NVIC priority register to have a value of 0x20 to increase the interrupt priority to allow the same interrupt to come again

2.3 Interrupt or task processing

2.4 Set NVIC priority register to have a value of 0x40 to bring back the priority to initial set value

2.5 exit from the interrupt

In the step 2.3, i create a delay of 10 milliseconds and expect the processor control to hit the entry point of the interrupt while it is within step 2.3. Please let me know if the expected behavior is possible with this microcontroller?

Regards,

Kishore

Re: Kinetis K65 interrupt nesting

mjbcswitzerland — Mon, 07 Jan 2019 03:56:49 GMT

That sounds right. Simplest thing to do is try it and then you can be sure.

Regards

Mark

Re: Kinetis K65 interrupt nesting

kishorebolisett — Mon, 07 Jan 2019 05:22:47 GMT

I have already tested the sequence, but I did not succeed in getting a overrun of the interrupt.

Regards,

Kishore

Re: Kinetis K65 interrupt nesting

mjbcswitzerland — Tue, 08 Jan 2019 00:49:12 GMT

Hi Kishore

Unfortunately I was probably wrong about the interrupt vector priority being able to interrupt itself.
When the PIT channel fires and its vector is taken the processor sets its "active interrupt vector" to its reference and although it is possible to get the second (higher priority) vector as a "pending vector" (see System Control Block's ICSR register where both are shown) the Cortex M4 doesn't look to allow a pending vector to be taken that is the same as the presently active vector.
As long as the pending vector is not equal to the active vector and the pending source's priority is higher than the active vector it is then indeed taken.

The only way that I can see the second being taken is to exit from its interrupt context, which sets the active vector back to zero and then it immediately re-enters.

Therefore it looks like you need to leave the initial interrupt context eg. using BX LR, which means that it is more complicated and requires a more traditional context switch where you swap the stacks beforehand.

As Kerry pointed out, the PIT has 4 channels, each with its own interrupt vector and so if you run multiple PITS in parallel you can then allow a second one to interrupt a first one's interrupt context by controlling the interrupt priorities of each channel.

The question is whether this is a good base for a scheduler or not?

Regards

Mark

Re: Kinetis K65 interrupt nesting

kishorebolisett — Tue, 08 Jan 2019 03:36:40 GMT

Hi Mark & Kerry – Definitely this behavior is not so friendly to be used for preemptive based schedulers which use single interrupt. I have used similar feature successfully on power-pc cores.

But thanks for all your guidance and support on this topic. I will try to figure out a way to handle overrun.

Regards,

Kishore