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    <title>topic Core Clock divide in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824417#M49846</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've got strange problem using SIM_CLKDIV1 to lower core clock on K80&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm running PLL on this board and i want to be able to divide&amp;nbsp;high PLL clocks to not exceed bus/core clocks limits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The problem is if i use this:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;SIM -&amp;gt; CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0)| //core&lt;BR /&gt; SIM_CLKDIV1_OUTDIV2(1)| // Busclk&lt;BR /&gt; SIM_CLKDIV1_OUTDIV3(3)| // FlexBus&lt;BR /&gt; SIM_CLKDIV1_OUTDIV4(7)); // Flash&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;It works, every clock is divided properly but if i try:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;SIM -&amp;gt; CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(1)| //core&lt;BR /&gt; SIM_CLKDIV1_OUTDIV2(1)| // Busclk&lt;BR /&gt; SIM_CLKDIV1_OUTDIV3(3)| // FlexBus&lt;BR /&gt; SIM_CLKDIV1_OUTDIV4(7)); // Flash&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Write is ignored and i end up with default values. Where is the catch? I read that maximum divide ratio between core and other clocks is 8 but i'm not exceeding this limitations&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for any help :smileyhappy:&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 10 Nov 2018 18:48:59 GMT</pubDate>
    <dc:creator>akimata</dc:creator>
    <dc:date>2018-11-10T18:48:59Z</dc:date>
    <item>
      <title>Core Clock divide</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824417#M49846</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've got strange problem using SIM_CLKDIV1 to lower core clock on K80&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm running PLL on this board and i want to be able to divide&amp;nbsp;high PLL clocks to not exceed bus/core clocks limits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The problem is if i use this:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;SIM -&amp;gt; CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0)| //core&lt;BR /&gt; SIM_CLKDIV1_OUTDIV2(1)| // Busclk&lt;BR /&gt; SIM_CLKDIV1_OUTDIV3(3)| // FlexBus&lt;BR /&gt; SIM_CLKDIV1_OUTDIV4(7)); // Flash&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;It works, every clock is divided properly but if i try:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;SIM -&amp;gt; CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(1)| //core&lt;BR /&gt; SIM_CLKDIV1_OUTDIV2(1)| // Busclk&lt;BR /&gt; SIM_CLKDIV1_OUTDIV3(3)| // FlexBus&lt;BR /&gt; SIM_CLKDIV1_OUTDIV4(7)); // Flash&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Write is ignored and i end up with default values. Where is the catch? I read that maximum divide ratio between core and other clocks is 8 but i'm not exceeding this limitations&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for any help :smileyhappy:&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 10 Nov 2018 18:48:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824417#M49846</guid>
      <dc:creator>akimata</dc:creator>
      <dc:date>2018-11-10T18:48:59Z</dc:date>
    </item>
    <item>
      <title>Re: Core Clock divide</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824418#M49847</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am using Clocks tool of MCUXpresso IDE, the GPIO example is able to run after modify the divider.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="GPIO example Clocks Tool default.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/74862i6F5880336D5889B9/image-size/large?v=v2&amp;amp;px=999" role="button" title="GPIO example Clocks Tool default.png" alt="GPIO example Clocks Tool default.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="GPIO example Clocks Tool modified.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/74792iD6328AE33C3C6CA0/image-size/large?v=v2&amp;amp;px=999" role="button" title="GPIO example Clocks Tool modified.png" alt="GPIO example Clocks Tool modified.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="SIM_CLKDIV1 debug.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/74793iF8D39E64097677AD/image-size/large?v=v2&amp;amp;px=999" role="button" title="SIM_CLKDIV1 debug.png" alt="SIM_CLKDIV1 debug.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Robin&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Nov 2018 09:00:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824418#M49847</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2018-11-12T09:00:08Z</dc:date>
    </item>
    <item>
      <title>Re: Core Clock divide</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824419#M49848</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;That's really usefull feature in MCUXpresso and now i'm able to set SIM_CLKDIV1 correctly but i noticed that's not perfect.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Not sure if it's bug or i'm doing something wrong but if i want to&amp;nbsp;clock my UART using this tool it's not working properly, wrong clock is selected.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How it's setuped:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="clocksx1.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/75569iD8F257DE075E1298/image-size/large?v=v2&amp;amp;px=999" role="button" title="clocksx1.JPG" alt="clocksx1.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Register values in clocks tab :&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="clockx2.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/75621i7D0AF8ABF314E06E/image-size/large?v=v2&amp;amp;px=999" role="button" title="clockx2.JPG" alt="clockx2.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What i get after i run the code:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="clockx3.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/75661i65D2BF28ECAEF020/image-size/large?v=v2&amp;amp;px=999" role="button" title="clockx3.JPG" alt="clockx3.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And the problem is not only when i want to use PLL to feed UART,&amp;nbsp;it always end up with&amp;nbsp;OSCERCLK clock.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Nov 2018 09:27:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824419#M49848</guid>
      <dc:creator>akimata</dc:creator>
      <dc:date>2018-11-16T09:27:31Z</dc:date>
    </item>
    <item>
      <title>Re: Core Clock divide</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824420#M49849</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please check if there is someplace else select the clock of LPUART again.&lt;BR /&gt;For example: the lpuart_interrupt will select OSCERCLK after BOARD_BootClockRUN&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="CLOCK_SetLpuartClock.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/76498i62550C161E7FEE38/image-size/large?v=v2&amp;amp;px=999" role="button" title="CLOCK_SetLpuartClock.png" alt="CLOCK_SetLpuartClock.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Robin&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Nov 2018 07:48:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Core-Clock-divide/m-p/824420#M49849</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2018-11-20T07:48:08Z</dc:date>
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