topic Re: K27 / K28 On-Chip RAM (OCRAM) Questions in Kinetis Microcontrollers

K27 / K28 On-Chip RAM (OCRAM) Questions

aes_mike — Tue, 02 Oct 2018 13:57:05 GMT

How does the performance of the OCRAM compare to the TCRAM (i.e. tightly coupled upper and lower SRAM chunks)? I cannot find any information regarding OCRAM in the K28 data sheet other than that it is there and it is located at 0x3400_0000 to 0x3407_FFFF.

Wondering how many CPU clock cycles per OCRAM cycle typical?

Is it 32-bits wide?

Thank you.

Re: K27 / K28 On-Chip RAM (OCRAM) Questions

victorjimenez — Wed, 10 Oct 2018 20:19:56 GMT

Hello,

The TCRAM is tightly coupled to the ARM Cortex-M4 core and the OCRAM is not tightly coupled to ARM Cortex-M4 core. The main benefit of the TCRAM it is, that the CPU can access it every clock cycle.

The OCRAM is accessed outside of the ARM Cortex-M4's platform via the AXBS crossbar. In the Crossbar Switch read and write transfers require two bus clock cycles. Additionally, these registers can be read from or written to only by 32-bit accesses. If you refer to chapter 20 of the reference manual you will find more information about the Crossbar Switch.

Hope it helps!

Victor.

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Re: K27 / K28 On-Chip RAM (OCRAM) Questions

aes_mike — Wed, 24 Oct 2018 01:04:24 GMT

Thank you Victor!

Mike