topic Re: K65P169M180SF5V2 GPIO Voltage Limits on Startup in Kinetis Microcontrollers

K65P169M180SF5V2 GPIO Voltage Limits on Startup

bhofer — Wed, 07 Nov 2018 14:01:55 GMT

Hi all!

Here is a question about the voltage limits of the K65P169M180SF5V2 GPIOs during startup.

Assuming that we have a peripheral powered with +5V and the K65 powered by an +3V3 LDO connected to this same +5V.

This periheral has a TX line connected via a voltage divider to an K65 GPIO that limits the input voltages to a safe level (max. ~3,3V).

In this situation the +5V can be present earlier at the voltage divider than the +3V3 supply at the K65, i.e. at startup the input voltage can be higher than the in datasheet specified VDIO_MAX of VDD+0.3V.

Other posts (https://community.nxp.com/thread/433880 ) clarify that the K-Series does not have protection diodes to VDD.

Therefore I assume, that in this situation the K65 works outside the safe specification and can be damaged, even if the series resistor of the voltage divider limits the current (e.g. <1mA).

Is this view correct or can the K65 tolerate such transient events?

Kind regards,

B.Hofer

Re: K65P169M180SF5V2 GPIO Voltage Limits on Startup

miduo — Thu, 08 Nov 2018 16:17:28 GMT

Hello,

You are correct that K65 can not "safe" working as the situation you mentioned. Even though this startup duration is short, we really do not recommend used as this case.

Re: K65P169M180SF5V2 GPIO Voltage Limits on Startup

bhofer — Mon, 12 Nov 2018 14:53:33 GMT

Thanks for the answer! So since this applies also to all analog pins, standard applications such as monitoring the device supply voltage (e.g. +5V or +12V over a voltage divider) face the same situation and require an external protection measure (e.g. diode to VDD and current limiting resistzor).

Why is this not clearly stated in the datasheet and instead hidden in some footnote?!