<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Assert RSTD will clear DTW bit field in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795240#M48418</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/pdrake"&gt;pdrake&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question:&lt;/P&gt;&lt;P&gt;System control register.&lt;BR /&gt;RSTD in the SYS CTRL register (PROCTL) - it’s not clearly documented that DTW bit gets cleared when this is asserted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Answer:&lt;/P&gt;&lt;P&gt;The following registers and bits are cleared by RSTD&lt;BR /&gt;• Data Port register&lt;BR /&gt;• Buffer is cleared and initialized.&lt;BR /&gt;• Present State register&lt;BR /&gt;• Buffer Read Enable&lt;BR /&gt;• Buffer Write Enable&lt;BR /&gt;• Read Transfer Active&lt;BR /&gt;• Write Transfer Active&lt;BR /&gt;• DATA Line Active&lt;BR /&gt;• Command Inhibit (DATA) Protocol Control register&lt;BR /&gt;• Continue Request&lt;BR /&gt;• Stop At Block Gap Request Interrupt Status register&lt;BR /&gt;• Buffer Read Ready&lt;BR /&gt;• Buffer Write Ready&lt;BR /&gt;• DMA Interrupt&lt;BR /&gt;• Block Gap Event&lt;BR /&gt;• Transfer Complete&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Setting SYS_CTRL[RSTD] will clear all the registers mentioned in the RSTD field description. DTW field will be clear if set, DTW is considering as PROT_Command Inhibit (DATA) Protocol Control Registers.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Aug 2018 16:30:04 GMT</pubDate>
    <dc:creator>tsi-chung_liew</dc:creator>
    <dc:date>2018-08-16T16:30:04Z</dc:date>
    <item>
      <title>Assert RSTD will clear DTW bit field</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795240#M48418</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/pdrake"&gt;pdrake&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question:&lt;/P&gt;&lt;P&gt;System control register.&lt;BR /&gt;RSTD in the SYS CTRL register (PROCTL) - it’s not clearly documented that DTW bit gets cleared when this is asserted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Answer:&lt;/P&gt;&lt;P&gt;The following registers and bits are cleared by RSTD&lt;BR /&gt;• Data Port register&lt;BR /&gt;• Buffer is cleared and initialized.&lt;BR /&gt;• Present State register&lt;BR /&gt;• Buffer Read Enable&lt;BR /&gt;• Buffer Write Enable&lt;BR /&gt;• Read Transfer Active&lt;BR /&gt;• Write Transfer Active&lt;BR /&gt;• DATA Line Active&lt;BR /&gt;• Command Inhibit (DATA) Protocol Control register&lt;BR /&gt;• Continue Request&lt;BR /&gt;• Stop At Block Gap Request Interrupt Status register&lt;BR /&gt;• Buffer Read Ready&lt;BR /&gt;• Buffer Write Ready&lt;BR /&gt;• DMA Interrupt&lt;BR /&gt;• Block Gap Event&lt;BR /&gt;• Transfer Complete&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Setting SYS_CTRL[RSTD] will clear all the registers mentioned in the RSTD field description. DTW field will be clear if set, DTW is considering as PROT_Command Inhibit (DATA) Protocol Control Registers.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Aug 2018 16:30:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795240#M48418</guid>
      <dc:creator>tsi-chung_liew</dc:creator>
      <dc:date>2018-08-16T16:30:04Z</dc:date>
    </item>
    <item>
      <title>Re: Assert RSTD will clear DTW bit field</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795241#M48419</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Hi Tc an Phlip,&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;This is still incorrect, incomplete and unclear:&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;The following registers and bits are cleared by RSTD&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Data Port register&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Buffer is cleared and initialized.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Present State register&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Buffer Read Enable&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Buffer Write Enable&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Read Transfer Active&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Write Transfer Active&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• DATA Line Active&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Command Inhibit (DATA) Protocol Control register&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Continue Request&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Stop At Block Gap Request Interrupt Status register&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Buffer Read Ready&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Buffer Write Ready&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• DMA Interrupt&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Block Gap Event&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• Transfer Complete&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;There are 1) formatting errors, 2) ambiguous names, and 3) not all bit are cleared in all registers.&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;1) Formatting:&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;The following registers and bits are cleared by RSTD&lt;BR /&gt;• Data Port register&lt;BR /&gt;• Buffer is cleared and initialized.&lt;BR /&gt;• Present State register&lt;BR /&gt;• Buffer Read Enable&lt;BR /&gt;• Buffer Write Enable&lt;BR /&gt;• Read Transfer Active&lt;BR /&gt;• Write Transfer Active&lt;BR /&gt;• DATA Line Active&lt;BR /&gt;• Command Inhibit (DATA) &lt;STRONG&gt;MISSING NEW LINE&amp;nbsp;&lt;/STRONG&gt;Protocol Control register&lt;BR /&gt;• Continue Request&lt;BR /&gt;• Stop At Block Gap Request &lt;STRONG&gt;MISSING NEW LINE&amp;nbsp;&lt;/STRONG&gt;Interrupt Status register&lt;BR /&gt;• Buffer Read Ready&lt;BR /&gt;• Buffer Write Ready&lt;BR /&gt;• DMA Interrupt&lt;BR /&gt;• Block Gap Event&lt;BR /&gt;• Transfer Complete&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;2) Search the manual for each of the above names. You will be frustrated to only find them in ONLY the one table.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;Using register names that result in unambiguous search results in the manual would be super helpful&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;like SDHC_SYSCTL or the full name and &lt;STRONG&gt;Buffer&lt;/STRONG&gt; Data Port register or better yet SDHC_DATPORT&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;3) Not all the bits in all the registers are cleared. The test is simple: a) set all the non-reserved bits in&amp;nbsp;SDHC_PROCTL b) assert&amp;nbsp;&amp;nbsp;SDHC_SYSCTL[RSTD] and c) read the results of&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;SDHC_PROCTL.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="color: #51626f;"&gt;The point I would like to reinforce, is that the documentation&amp;nbsp;can only add value for the end user if it is an unambiguous&amp;nbsp;reference.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="color: #51626f;"&gt;If I had described the test above as: do the reset and read the register. Would that be clear? What reset? System reset POR on reset or&amp;nbsp;&lt;SPAN style="background-color: #ffffff;"&gt;SDHC_SYSCTL[RSTD]?&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;David&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Aug 2018 17:21:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795241#M48419</guid>
      <dc:creator>davidsidrane</dc:creator>
      <dc:date>2018-08-16T17:21:10Z</dc:date>
    </item>
    <item>
      <title>Re: Assert RSTD will clear DTW bit field</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795242#M48420</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The above is in reference to&amp;nbsp;&lt;/P&gt;&lt;P&gt;K66 Sub-Family Reference Manual&lt;BR /&gt;Supports: MK66FN2M0VMD18, MK66FX1M0VMD18,&lt;BR /&gt;MK66FN2M0VLQ18, MK66FX1M0VLQ18,&lt;BR /&gt;Document Number: K66P144M180SF5RMV2&lt;BR /&gt;Rev. 2, May 2015&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Aug 2018 09:17:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Assert-RSTD-will-clear-DTW-bit-field/m-p/795242#M48420</guid>
      <dc:creator>davidsidrane</dc:creator>
      <dc:date>2018-08-17T09:17:25Z</dc:date>
    </item>
  </channel>
</rss>

