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    <title>topic Re: Access to peripherals in UserMode when K82 MPU is enabled in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792896#M48227</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Xiangjun Rong !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thank you ! It is really work like this. It have sense to add AIPS table to each TCB of FreeRTOS for get more secure execution&amp;nbsp; environment.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;I have few small questions about K82 after that.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;1.&amp;nbsp; So it is dosn't have sense to protect by MPU areas after 0x40000000 where peripherals starts ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp; &amp;nbsp; Core always have access to this area and only AIPS0/AIPS1 blocks can be used for protect peripheral memory mapped area ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;2.&amp;nbsp;Private Peripherals at address &amp;gt;= 0xE00000000 is always accessible by core in privileged mode and MPU settings dosn't have any effect as well.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;By the way , do you have any application note where all peripherals what have effect to security is explained for K82 ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;What should be hardened for get from K82 as max protection as possible ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Eugene&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 20 Jun 2018 12:51:31 GMT</pubDate>
    <dc:creator>EugeneHiihtaja</dc:creator>
    <dc:date>2018-06-20T12:51:31Z</dc:date>
    <item>
      <title>Access to peripherals in UserMode when K82 MPU is enabled</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792894#M48225</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is not so clear from documentation if K82 MPU can be configured for access to simple peripherals (LPUART0 )&lt;/P&gt;&lt;P&gt;in UserMode. All trials to configure LPUART address space in MPU for read/write space dosn't have any effect and simple read of DATA register cause BusFault.&lt;/P&gt;&lt;P&gt;Not all ARM can grant access for this area in UserMode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But what about K82 ?&lt;/P&gt;&lt;P&gt;Does it possible to configure K82 MPU if in UserMode to have access to LPUART0 and i2C address space ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Jun 2018 16:27:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792894#M48225</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2018-06-18T16:27:44Z</dc:date>
    </item>
    <item>
      <title>Re: Access to peripherals in UserMode when K82 MPU is enabled</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792895#M48226</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Eugene,&lt;/P&gt;&lt;P&gt;I think the MPU module is used to protect memory rather than the peripheral as the name MPU&amp;nbsp; implies "memory protection unit".&lt;/P&gt;&lt;P&gt;If you access the peripheral, you can set the AIPSx_PACRn and AIPSx_MPRA register to protect the peripheral.&lt;/P&gt;&lt;P&gt;The LPUART0&amp;nbsp; module locates at slot 68 of AIPS1 as the Table 5-3. Peripheral bridge 1 slot assignments (continued) which I display as the screenshot.&lt;/P&gt;&lt;P&gt;You can write the AIPS1_PACR68 to set the access right for the LPUART0. You can set the AIPS1_MPRA to configure the different master access right.&lt;/P&gt;&lt;P&gt;Hope it can help you&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Xiangjun Rong&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/62113iBB77ED2CB8FF9DCD/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Jun 2018 09:38:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792895#M48226</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2018-06-20T09:38:31Z</dc:date>
    </item>
    <item>
      <title>Re: Access to peripherals in UserMode when K82 MPU is enabled</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792896#M48227</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Xiangjun Rong !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thank you ! It is really work like this. It have sense to add AIPS table to each TCB of FreeRTOS for get more secure execution&amp;nbsp; environment.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;I have few small questions about K82 after that.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;1.&amp;nbsp; So it is dosn't have sense to protect by MPU areas after 0x40000000 where peripherals starts ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp; &amp;nbsp; Core always have access to this area and only AIPS0/AIPS1 blocks can be used for protect peripheral memory mapped area ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;2.&amp;nbsp;Private Peripherals at address &amp;gt;= 0xE00000000 is always accessible by core in privileged mode and MPU settings dosn't have any effect as well.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;By the way , do you have any application note where all peripherals what have effect to security is explained for K82 ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;What should be hardened for get from K82 as max protection as possible ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Eugene&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Jun 2018 12:51:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Access-to-peripherals-in-UserMode-when-K82-MPU-is-enabled/m-p/792896#M48227</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2018-06-20T12:51:31Z</dc:date>
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