Kinetis MicrocontrollersのトピックRe: DTCM/ITCM Aliasing? (KV5X)

DTCM/ITCM Aliasing? (KV5X)

lsrbigfoot — Fri, 02 Feb 2018 17:43:51 GMT

While using the K20/K22 (cortex-M4), I have been using bit-banding macros to access the aliased region for SRAM_U (0x20000000 to 0x2000FFFF).

Example Macro:
#define BandAddr 0x22000000
#define BitBandMem(Addr, Bit) (*(volatile uint32_t*)(BandAddr + ((((uint32_t)Addr) & 0x3FF) << 5) + (((uint8_t)Bit) << 2)))

Does the KV5X (Cortex-M7) support bit-banding to both ITCM and DTCM memories (D0TCM and D1TCM) if I were to use similar macros?

Re: DTCM/ITCM Aliasing? (KV5X)

chris_brown — Mon, 12 Feb 2018 19:49:54 GMT

Hi lsrbigfoot,

So not natively. There is no aliased region for the ITCM or DTCM areas to write to.

But we did implement the BME2 engine for just such a request. You should be able to find the necessary information in chapter 24 of the KV5x reference manual, as well as some examples. Please let me know if you have further questions about that.

Best regards,

Chris