<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic K64 TX FIFO Underflow EDMA SPI Slave in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778940#M47388</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a K64 SPI Slave using EDMA drivers from KSDK 1.3.0. The SPI master is sending 8K blocks of data (MODE0, 16 bit words) with a 10MHz SPI clock in what appears to be 128 byte bursts. My highest priority MQX task is spinning in a while loop waiting for 8K blocks of data from the master using call to DSPI_DRV_EdmaSlaveTransferBlocking. The master waits 2 milliseconds in between transfers and I have verified that the K64 is always ready to receive before the master initiates a transfer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I turned on RX FIFO Overflow and TX FIFO Underflow interrupts because I was losing SPI data between master/slave. I am occasionally getting TX FIFO Underflow interrupts to occur. I added error handling and early abort to the &lt;SPAN&gt;DSPI_DRV_EdmaSlaveTransferBlocking&amp;nbsp;&lt;/SPAN&gt;API function so that I can recover from this condition, but I would like to know why this interrupt is occurring so that I may attempt to fix the problem. My understanding is that the DSPI/EDMA transfers are completely hardware driven at this point.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The K64 is running at 120MHz with a 60MHz bus clock.&amp;nbsp; I am using DSPI channel 0 in DMA mode. I have fixed priority DMA channels 0 and 1 for RX and TX respectively. The DMA interrupts are both set to high priority. No other peripherals&amp;nbsp; (UART, I2C, etc.) are active during the SPI transfers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;All peripherals are configured using Processor Expert.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 Dec 2017 20:23:48 GMT</pubDate>
    <dc:creator>adamkent</dc:creator>
    <dc:date>2017-12-11T20:23:48Z</dc:date>
    <item>
      <title>K64 TX FIFO Underflow EDMA SPI Slave</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778940#M47388</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a K64 SPI Slave using EDMA drivers from KSDK 1.3.0. The SPI master is sending 8K blocks of data (MODE0, 16 bit words) with a 10MHz SPI clock in what appears to be 128 byte bursts. My highest priority MQX task is spinning in a while loop waiting for 8K blocks of data from the master using call to DSPI_DRV_EdmaSlaveTransferBlocking. The master waits 2 milliseconds in between transfers and I have verified that the K64 is always ready to receive before the master initiates a transfer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I turned on RX FIFO Overflow and TX FIFO Underflow interrupts because I was losing SPI data between master/slave. I am occasionally getting TX FIFO Underflow interrupts to occur. I added error handling and early abort to the &lt;SPAN&gt;DSPI_DRV_EdmaSlaveTransferBlocking&amp;nbsp;&lt;/SPAN&gt;API function so that I can recover from this condition, but I would like to know why this interrupt is occurring so that I may attempt to fix the problem. My understanding is that the DSPI/EDMA transfers are completely hardware driven at this point.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The K64 is running at 120MHz with a 60MHz bus clock.&amp;nbsp; I am using DSPI channel 0 in DMA mode. I have fixed priority DMA channels 0 and 1 for RX and TX respectively. The DMA interrupts are both set to high priority. No other peripherals&amp;nbsp; (UART, I2C, etc.) are active during the SPI transfers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;All peripherals are configured using Processor Expert.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Dec 2017 20:23:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778940#M47388</guid>
      <dc:creator>adamkent</dc:creator>
      <dc:date>2017-12-11T20:23:48Z</dc:date>
    </item>
    <item>
      <title>Re: K64 TX FIFO Underflow EDMA SPI Slave</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778941#M47389</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Adam:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please refer to the known issue of MQX SPI driver,&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/2494iB737F51F897DBABD/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I would suggest you check whether DSPI is the only user of eDMA.&amp;nbsp;&amp;nbsp; Since you are using eDMA for rx and tx, you can disable tx edma or rx edma to see whether it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 Jan 2018 05:01:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778941#M47389</guid>
      <dc:creator>danielchen</dc:creator>
      <dc:date>2018-01-12T05:01:05Z</dc:date>
    </item>
    <item>
      <title>Re: K64 TX FIFO Underflow EDMA SPI Slave</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778942#M47390</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Daniel,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for the response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Just to be perfectly clear...It sounds like even though the DSPI is the only user of the eDMA in my case, I may still have problems if I try to use eDMA for both RX &lt;SPAN style="text-decoration: underline;"&gt;AND&lt;/SPAN&gt; TX and that I can only use eDMA for one or the other. Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks again,&lt;/P&gt;&lt;P&gt;Adam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Feb 2018 19:41:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-TX-FIFO-Underflow-EDMA-SPI-Slave/m-p/778942#M47390</guid>
      <dc:creator>adamkent</dc:creator>
      <dc:date>2018-02-08T19:41:36Z</dc:date>
    </item>
  </channel>
</rss>

