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    <title>topic Re: KW21Z Memory Map Inconsistency in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775321#M47178</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Gerardo,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This makes sense, thanks for the explanation!&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 18 Jun 2018 18:36:29 GMT</pubDate>
    <dc:creator>neal_jackson</dc:creator>
    <dc:date>2018-06-18T18:36:29Z</dc:date>
    <item>
      <title>KW21Z Memory Map Inconsistency</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775319#M47176</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In the reference manual, it indicates that the KW41Z/31Z/21Z all have their RAM region start at 0x1FFF8000. The linker scripts generated for the KW21Z 256/64 when using MCUXpresso uses 0x1FFFC000 instead. Linker scripts generated for the KW41Z have RAM at the expected &lt;SPAN&gt;0x1FFF8000&lt;/SPAN&gt;. My application hits a hard fault immediately if I change this to&amp;nbsp;&lt;SPAN&gt;0x1FFF8000 as mentioned in the reference manual.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Why is this different for the KW21Z 256/64? Does this mean the amount of available RAM is less than 64KB?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks for any insight you can give.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Jun 2018 00:07:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775319#M47176</guid>
      <dc:creator>neal_jackson</dc:creator>
      <dc:date>2018-06-13T00:07:11Z</dc:date>
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    <item>
      <title>Re: KW21Z Memory Map Inconsistency</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775320#M47177</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&amp;nbsp;Neal Jackson,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The&amp;nbsp;MKW21Z&lt;STRONG&gt;256&lt;/STRONG&gt;VHT4 has 256 KB Flash and 64 KB SRAM, as indicated by &lt;STRONG&gt;Table 1-1&lt;/STRONG&gt;. in the &lt;A href="https://www.nxp.com/docs/en/reference-manual/MKW41Z512RM.pdf"&gt;RM&lt;/A&gt;.&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/61939i85DDAAD7F29EBC31/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The address ranges are dependent on the size of the SRAM, where the SRAM_L region contains 1/4 of the total SRAM and the SRAM_U contains the other 3/4. So, the valid address ranges for SRAM_L and SRAM_U are then defined as:&lt;BR /&gt;• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF&lt;BR /&gt;• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Resulting in:&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;• SRAM_L = 0x1FFF_C000 to 0x1FFF_FFFF&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;• SRAM_U = 0x2000_0000 to&amp;nbsp;0x2000_BFFF&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;This is why MCUXpresso uses 0x1FFFC000 and will hit a hardfault if you change it to&amp;nbsp;0x1FFF8000.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Hope this helps!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Gerardo&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Jun 2018 16:37:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775320#M47177</guid>
      <dc:creator>gerardo_rodriguez</dc:creator>
      <dc:date>2018-06-18T16:37:26Z</dc:date>
    </item>
    <item>
      <title>Re: KW21Z Memory Map Inconsistency</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775321#M47178</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Gerardo,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This makes sense, thanks for the explanation!&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Jun 2018 18:36:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/KW21Z-Memory-Map-Inconsistency/m-p/775321#M47178</guid>
      <dc:creator>neal_jackson</dc:creator>
      <dc:date>2018-06-18T18:36:29Z</dc:date>
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