Understanding Programmable Delay Block (PDB) details

maelh — Mon, 02 Nov 2020 14:07:52 GMT

Hello,

I have a MK66FX1M0VMD18 chip from NXP/Freescale and was trying to understand/confirm my understanding of the PDB in more detail. Sorry if I am asking something obvious. (Since there is just one PDB in this chip, I'll use PDB0 instead of PDBx for the identifier names.)

Interrupts are generated at the expected frequency, when I set the frequency of the PDB clock using the PRESCALER and MULT fields in the PDB0_SC register, then set the PDB0_MOD register to the desired modulus to divide this clock even finer, and also set PDB_SC_PDBIE.

Now what I do not understand exactly is the functioning of the PDB0_IDLY register. As far as I understood the internal counter of the PDB (PDB0_CNT) is incremented at each PDB clock tick, and the PDB clock is generated from the peripheral frequency divided by the prescaler divider (which itself is set by MULT and PRESCALER).

PDB0_MOD sets the modulus for the PDB0_CNT, so when PDB0_CNT reaches this value, PDB0_CNT resets to zero and the interrupt/dma request is triggered. PDB0_IDLY determines at which value of PDB0_CNT the interrupt or dma request is triggered.

In pseudocode:

at_every_PDB_clock_tick:
    if (PDB0_CNT == PDB0_MOD + 1)
      PDB0_CNT = 0;
    if (PDB0_CNT == PDB0_IDLY)
      trigger_interrupt_or_DMA_request();
    PDB0_CNT++;‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

If anything is wrong so far, please correct me (in pseudocode would be great, to have it clearer than using just language). For example, I am not sure if the interrupt/dma gets triggered already at the start, or only after the PDB0_CNT cycled once at least. So, assume PDB0_MOD = 9 and PDB0_IDLY = 0: would it already trigger an interrupt immediately when the PDB is started, and the counter PDB0_CNT had no time to increment yet? Or would it wait until the PDB0 counter is reset to zero again due to having completed one cycle as defined by PDB0_MOD?

A related question: in the documentation, for example page 1116, the following is said "Reading this field returns the value of internal register that is effective for the current cycle of the PDB.". Is the mentioned cycle the cycle PDB0_CNT does, from 0 to PDB0_MOD?

Which leads me to my final question. If all of the above is true, you can change PDB0_IDLY in the current cycle, and it will only be applied in the next cycle? You could do PWM this way with a stable frequency, but variable duty cycle.

If you made it this far, thanks for your patience

Re: Understanding Programmable Delay Block (PDB) details

mjbcswitzerland — Wed, 31 Jan 2018 22:58:05 GMT

See http://www.utasker.com/docs/uTasker/uTaskerADC.pdf - page 9, which may help clarify something.

Regards

Mark

Kinetis: http://www.utasker.com/kinetis.html
Kinetis K66:
- http://www.utasker.com/kinetis/TWR-K65F180M.html
- http://www.utasker.com/kinetis/FRDM-K66F.html
- http://www.utasker.com/kinetis/TEENSY_3.6.html

Free Open Source solution: https://github.com/uTasker/uTasker-Kinetis
Working project in 15 minutes video: https://youtu.be/K8ScSgpgQ6M

For better, faster, cheaper product developments consider the uTasker developer's version, professional Kinetis support, one-on-one training and complete fast-track project solutions to set you apart from the herd : http://www.utasker.com/support.html

Re: Understanding Programmable Delay Block (PDB) details

maelh — Mon, 05 Feb 2018 02:04:41 GMT

Thanks. I am still not clear about all the details, as they aren't mentioned explicitly, but your document helped clear up some terms.

Kinetis MicrocontrollersのトピックUnderstanding Programmable Delay Block (PDB) details

Understanding Programmable Delay Block (PDB) details

Re: Understanding Programmable Delay Block (PDB) details

Re: Understanding Programmable Delay Block (PDB) details